[llvm] 9d1ff78 - [AArch64] Add support for the Cortex-X3 CPU
Victor Campos via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 9 03:33:56 PST 2022
Author: Victor Campos
Date: 2022-11-09T11:33:48Z
New Revision: 9d1ff787e5c2b19e19e5475b9c36f4e5c2a07d23
URL: https://github.com/llvm/llvm-project/commit/9d1ff787e5c2b19e19e5475b9c36f4e5c2a07d23
DIFF: https://github.com/llvm/llvm-project/commit/9d1ff787e5c2b19e19e5475b9c36f4e5c2a07d23.diff
LOG: [AArch64] Add support for the Cortex-X3 CPU
Cortex-X3 is an Armv9-A AArch64 CPU.
This patch introduces support for Cortex-X3.
Technical Reference Manual: https://developer.arm.com/documentation/101593/latest
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136589
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/test/Driver/aarch64-mcpu.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/lib/Support/Host.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 0d464e9fb7d51..774b575b52609 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -744,11 +744,11 @@ Arm and AArch64 Support in Clang
- ``-march`` values for targeting armv2, armv2A, armv3 and armv3M have been removed.
Their presence gave the impression that Clang can correctly generate code for
them, which it cannot.
-- Add driver and tuning support for Neoverse V2 via the flag ``-mcpu=neoverse-v2``.
- Native detection is also supported via ``-mcpu=native``.
- Support has been added for the following processors (-mcpu identifiers in parenthesis):
* Arm Cortex-A715 (cortex-a715).
+ * Arm Cortex-X3 (cortex-x3).
+ * Arm Neoverse V2 (neoverse-v2)
Floating Point Support in Clang
-------------------------------
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index b40c579acdf00..d0f898357570a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -41,6 +41,8 @@
// CORTEXX1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1"
// RUN: %clang -target aarch64 -mcpu=cortex-x1c -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXX1C %s
// CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
+// RUN: %clang -target aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXX3 %s
+// CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
// RUN: %clang -target aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXA78 %s
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
// RUN: %clang -target aarch64 -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A78C %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 1d7d89ebb1eb0..f48a54d452f68 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
+// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 3a8c5b079a9e0..d71974da47a45 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -103,6 +103,7 @@ Changes to the AArch64 Backend
------------------------------
* Added support for the Cortex-A715 CPU.
+* Added support for the Cortex-X3 CPU.
Changes to the AMDGPU Backend
-----------------------------
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index e1792a57e35e0..847b54c7a1d49 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -225,6 +225,12 @@ AARCH64_CPU_NAME("cortex-x2", ARMV9A, FK_NEON_FP_ARMV8, false,
AArch64::AEK_PAUTH | AArch64::AEK_SSBS | AArch64::AEK_SB |
AArch64::AEK_SVE | AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
AArch64::AEK_FP16FML))
+AARCH64_CPU_NAME("cortex-x3", ARMV9A, FK_NEON_FP_ARMV8, false,
+ (AArch64::AEK_SVE | AArch64::AEK_PERFMON | AArch64::AEK_PROFILE |
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_MTE |
+ AArch64::AEK_SVE2BITPERM | AArch64::AEK_SB | AArch64::AEK_PAUTH |
+ AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_PREDRES |
+ AArch64::AEK_FLAGM | AArch64::AEK_SSBS))
AARCH64_CPU_NAME("neoverse-e1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
AArch64::AEK_RCPC | AArch64::AEK_SSBS))
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index fa291e9cccd69..cff9142f59786 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -216,6 +216,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
.Case("0xd4d", "cortex-a715")
.Case("0xd44", "cortex-x1")
.Case("0xd4c", "cortex-x1c")
+ .Case("0xd4e", "cortex-x3")
.Case("0xd0c", "neoverse-n1")
.Case("0xd49", "neoverse-n2")
.Case("0xd40", "neoverse-v1")
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index f28f460ea4e72..e8ff26fbb23a1 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -799,6 +799,13 @@ def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
FeatureLSLFast,
FeaturePostRAScheduler]>;
+def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3",
+ "Cortex-X3 ARM processors", [
+ FeatureLSLFast,
+ FeatureFuseAdrpAdd,
+ FeatureFuseAES,
+ FeaturePostRAScheduler]>;
+
def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
"Fujitsu A64FX processors", [
FeaturePostRAScheduler,
@@ -1127,6 +1134,11 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML];
+ list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON,
+ FeaturePerfMon, FeatureETE, FeatureTRBE,
+ FeatureSPE, FeatureBF16, FeatureMatMulInt8,
+ FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
+ FeatureFP16FML];
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
FeatureSVE, FeatureComplxNum];
@@ -1259,6 +1271,8 @@ def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
[TuneX1]>;
def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2,
[TuneX2]>;
+def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3,
+ [TuneX3]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model,
ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
def : ProcessorModel<"neoverse-n1", CortexA57Model,
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 4acf8a1bf8603..e54f54b057917 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -144,6 +144,7 @@ void AArch64Subtarget::initializeProperties() {
case CortexA710:
case CortexA715:
case CortexX2:
+ case CortexX3:
PrefFunctionLogAlignment = 4;
VScaleForTuning = 1;
PrefLoopLogAlignment = 5;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 4718a01ad2166..c28bf11ec4cf2 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -69,6 +69,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
CortexX1,
CortexX1C,
CortexX2,
+ CortexX3,
ExynosM3,
Falkor,
Kryo,
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index dd4e5fcd0fa22..1e0dc3381fffb 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1086,6 +1086,19 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SVE2BITPERM | AArch64::AEK_SSBS |
AArch64::AEK_SB | AArch64::AEK_FP16FML,
"9-A"),
+ ARMCPUTestParams("cortex-x3", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_BF16 |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_MTE | AArch64::AEK_PAUTH |
+ AArch64::AEK_SVE | AArch64::AEK_SVE2 |
+ AArch64::AEK_SVE2BITPERM | AArch64::AEK_SB |
+ AArch64::AEK_PROFILE | AArch64::AEK_PERFMON |
+ AArch64::AEK_I8MM | AArch64::AEK_FP16 |
+ AArch64::AEK_FP16FML | AArch64::AEK_PREDRES |
+ AArch64::AEK_FLAGM | AArch64::AEK_SSBS,
+ "9-A"),
ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1309,7 +1322,7 @@ INSTANTIATE_TEST_SUITE_P(
"8.2-A")));
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 60;
+static constexpr unsigned NumAArch64CPUArchs = 61;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
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