[PATCH] D137689: [AArch64] Select BFI/BFXIL to ORR with shifted operand when one operand is the left or right shift of another operand

[Mingming Liu via Phabricator via llvm-commits]

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Use right shift [1] as an example

- Before, bfxil is generated (https://godbolt.org/z/EfzWMszPn)
- After, orr with right-shifted operand is generated (added test cases in `CodeGen/AArch64/bitfield-insert.ll`)

[1]

  define i64 @test_orr_not_bfxil_i64(i64 %0) {
    %2 = and i64 %0, 1044480 ; 0xff000
    %3 = lshr i64 %2, 12
    %4 = or i64 %2, %3
    ret i64 %4
  }


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137689

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/bitfield-insert.ll

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