[lld] 640d9b3 - [lld] Fix duplicate word typos. NFC

Fangrui Song via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 8 17:28:09 PST 2022


Author: Fangrui Song
Date: 2022-11-08T17:28:04-08:00
New Revision: 640d9b3296b6290eb7f65783a9a77b9851bd9745

URL: https://github.com/llvm/llvm-project/commit/640d9b3296b6290eb7f65783a9a77b9851bd9745
DIFF: https://github.com/llvm/llvm-project/commit/640d9b3296b6290eb7f65783a9a77b9851bd9745.diff

LOG: [lld] Fix duplicate word typos. NFC

Based on lld/ part of D137338 but reflowed comments.

Added: 
    

Modified: 
    lld/COFF/DebugTypes.cpp
    lld/COFF/PDB.cpp
    lld/MachO/Driver.cpp
    lld/MachO/ICF.cpp
    lld/MachO/InputFiles.cpp
    lld/MachO/UnwindInfoSection.cpp
    lld/test/ELF/arm-fix-cortex-a8-toolarge.s
    lld/wasm/Writer.cpp

Removed: 
    


################################################################################
diff  --git a/lld/COFF/DebugTypes.cpp b/lld/COFF/DebugTypes.cpp
index 31618cced57a9..ff469685fb7fa 100644
--- a/lld/COFF/DebugTypes.cpp
+++ b/lld/COFF/DebugTypes.cpp
@@ -823,10 +823,9 @@ void UsePrecompSource::loadGHashes() {
   if (!pchSrc)
     return;
 
-  // To compute ghashes of a /Yu object file, we need to build on the the
-  // ghashes of the /Yc PCH object. After we are done hashing, discard the
-  // ghashes from the PCH source so we don't unnecessarily try to deduplicate
-  // them.
+  // To compute ghashes of a /Yu object file, we need to build on the ghashes of
+  // the /Yc PCH object. After we are done hashing, discard the ghashes from the
+  // PCH source so we don't unnecessarily try to deduplicate them.
   std::vector<GloballyHashedType> hashVec =
       pchSrc->ghashes.take_front(precompDependency.getTypesCount());
   forEachTypeChecked(file->debugTypes, [&](const CVType &ty) {

diff  --git a/lld/COFF/PDB.cpp b/lld/COFF/PDB.cpp
index 2da63ab4e59a9..ad1468711ddcf 100644
--- a/lld/COFF/PDB.cpp
+++ b/lld/COFF/PDB.cpp
@@ -119,7 +119,7 @@ class PDBLinker {
                                std::vector<StringTableFixup> &stringTableFixups,
                                BinaryStreamRef symData);
 
-  // Write all module symbols from all all live debug symbol subsections of the
+  // Write all module symbols from all live debug symbol subsections of the
   // given object file into the given stream writer.
   Error writeAllModuleSymbolRecords(ObjFile *file, BinaryStreamWriter &writer);
 

diff  --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp
index 9875c6f29a608..07db434260d84 100644
--- a/lld/MachO/Driver.cpp
+++ b/lld/MachO/Driver.cpp
@@ -1383,11 +1383,11 @@ bool macho::link(ArrayRef<const char *> argsArr, llvm::raw_ostream &stdoutOS,
     uint64_t pagezeroSize = args::getHex(args, OPT_pagezero_size, 0);
 
     // ld64 does something really weird. It attempts to realign the value to the
-    // page size, but assumes the the page size is 4K. This doesn't work with
-    // most of Apple's ARM64 devices, which use a page size of 16K. This means
-    // that it will first 4K align it by rounding down, then round up to 16K.
-    // This probably only happened because no one using this arg with anything
-    // other then 0, so no one checked if it did what is what it says it does.
+    // page size, but assumes the page size is 4K. This doesn't work with most
+    // of Apple's ARM64 devices, which use a page size of 16K. This means that
+    // it will first 4K align it by rounding down, then round up to 16K.  This
+    // probably only happened because no one using this arg with anything other
+    // then 0, so no one checked if it did what is what it says it does.
 
     // So we are not copying this weird behavior and doing the it in a logical
     // way, by always rounding down to page size.

diff  --git a/lld/MachO/ICF.cpp b/lld/MachO/ICF.cpp
index bc3dd99ccc459..3dfc46412e842 100644
--- a/lld/MachO/ICF.cpp
+++ b/lld/MachO/ICF.cpp
@@ -436,7 +436,7 @@ void macho::foldIdenticalSections(bool onlyCfStrings) {
       // Some sections have embedded addends that foil ICF's hashing / equality
       // checks. (We can ignore embedded addends when doing ICF because the same
       // information gets recorded in our Reloc structs.) We therefore create a
-      // mutable copy of the the section data and zero out the embedded addends
+      // mutable copy of the section data and zero out the embedded addends
       // before performing any hashing / equality checks.
       if (isFoldableWithAddendsRemoved) {
         // We have to do this copying serially as the BumpPtrAllocator is not

diff  --git a/lld/MachO/InputFiles.cpp b/lld/MachO/InputFiles.cpp
index 57b98312ed274..db7050fef2f79 100644
--- a/lld/MachO/InputFiles.cpp
+++ b/lld/MachO/InputFiles.cpp
@@ -519,16 +519,15 @@ void ObjFile::parseRelocations(ArrayRef<SectionHeader> sectionHeaders,
     // ARM64_RELOC_BRANCH26 or ARM64_RELOC_PAGE21/PAGEOFF12 holds the
     // base symbolic address.
     //
-    // Note: X86 does not use *_RELOC_ADDEND because it can embed an
-    // addend into the instruction stream. On X86, a relocatable address
-    // field always occupies an entire contiguous sequence of byte(s),
-    // so there is no need to merge opcode bits with address
-    // bits. Therefore, it's easy and convenient to store addends in the
-    // instruction-stream bytes that would otherwise contain zeroes. By
-    // contrast, RISC ISAs such as ARM64 mix opcode bits with with
-    // address bits so that bitwise arithmetic is necessary to extract
-    // and insert them. Storing addends in the instruction stream is
-    // possible, but inconvenient and more costly at link time.
+    // Note: X86 does not use *_RELOC_ADDEND because it can embed an addend into
+    // the instruction stream. On X86, a relocatable address field always
+    // occupies an entire contiguous sequence of byte(s), so there is no need to
+    // merge opcode bits with address bits. Therefore, it's easy and convenient
+    // to store addends in the instruction-stream bytes that would otherwise
+    // contain zeroes. By contrast, RISC ISAs such as ARM64 mix opcode bits with
+    // address bits so that bitwise arithmetic is necessary to extract and
+    // insert them. Storing addends in the instruction stream is possible, but
+    // inconvenient and more costly at link time.
 
     relocation_info relInfo = relInfos[i];
     bool isSubtrahend =

diff  --git a/lld/MachO/UnwindInfoSection.cpp b/lld/MachO/UnwindInfoSection.cpp
index 1dfa6ecca1f4c..b83aa896b1527 100644
--- a/lld/MachO/UnwindInfoSection.cpp
+++ b/lld/MachO/UnwindInfoSection.cpp
@@ -262,7 +262,7 @@ void UnwindInfoSectionImpl::prepareRelocations(ConcatInputSection *isec) {
       // application provides its own personality function, it might be
       // referenced by an extern Defined symbol reloc, or a local section reloc.
       if (auto *defined = dyn_cast<Defined>(s)) {
-        // XXX(vyng) This is a a special case for handling duplicate personality
+        // XXX(vyng) This is a special case for handling duplicate personality
         // symbols. Note that LD64's behavior is a bit 
diff erent and it is
         // inconsistent with how symbol resolution usually work
         //
@@ -571,10 +571,9 @@ void UnwindInfoSectionImpl::finalize() {
     }
     page.entryCount = i - page.entryIndex;
 
-    // If this is not the final page, see if it's possible to fit more
-    // entries by using the regular format. This can happen when there
-    // are many unique encodings, and we we saturated the local
-    // encoding table early.
+    // If this is not the final page, see if it's possible to fit more entries
+    // by using the regular format. This can happen when there are many unique
+    // encodings, and we saturated the local encoding table early.
     if (i < cuIndices.size() &&
         page.entryCount < REGULAR_SECOND_LEVEL_ENTRIES_MAX) {
       page.kind = UNWIND_SECOND_LEVEL_REGULAR;

diff  --git a/lld/test/ELF/arm-fix-cortex-a8-toolarge.s b/lld/test/ELF/arm-fix-cortex-a8-toolarge.s
index 3937fc3d0eb85..d80673b35953c 100644
--- a/lld/test/ELF/arm-fix-cortex-a8-toolarge.s
+++ b/lld/test/ELF/arm-fix-cortex-a8-toolarge.s
@@ -38,7 +38,7 @@ target:
 target2:
  .section .text.02, "ax", %progbits
 /// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit
-/// non branch instruction, a patch will be be attempted. Unfortunately the
+/// non branch instruction, a patch will be attempted. Unfortunately the
 /// the BL cannot reach outside the section so we have to abort the patch.
  nop.w
  bl target2

diff  --git a/lld/wasm/Writer.cpp b/lld/wasm/Writer.cpp
index 95061ab22a260..4e83b10afddbc 100644
--- a/lld/wasm/Writer.cpp
+++ b/lld/wasm/Writer.cpp
@@ -1084,13 +1084,13 @@ void Writer::createInitMemoryFunction() {
   {
     raw_string_ostream os(bodyContent);
     // Initialize memory in a thread-safe manner. The thread that successfully
-    // increments the flag from 0 to 1 is is responsible for performing the
-    // memory initialization. Other threads go sleep on the flag until the
-    // first thread finishing initializing memory, increments the flag to 2,
-    // and wakes all the other threads. Once the flag has been set to 2,
-    // subsequently started threads will skip the sleep. All threads
-    // unconditionally drop their passive data segments once memory has been
-    // initialized. The generated code is as follows:
+    // increments the flag from 0 to 1 is responsible for performing the memory
+    // initialization. Other threads go sleep on the flag until the first thread
+    // finishing initializing memory, increments the flag to 2, and wakes all
+    // the other threads. Once the flag has been set to 2, subsequently started
+    // threads will skip the sleep. All threads unconditionally drop their
+    // passive data segments once memory has been initialized. The generated
+    // code is as follows:
     //
     // (func $__wasm_init_memory
     //  (block $drop


        


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