[PATCH] D137670: [PowerPC] Switch to by-name matching for instructions (part 2 of 2).

[James Y Knight via Phabricator via llvm-commits]

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Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

Also memrix

Also memrix16

Also memri34

Also memrihash and spe*disp

Remove useDeprecatedPositionallyEncodedOperands


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137670

Files:
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrFormats.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrP10.td
  llvm/lib/Target/PowerPC/PPCInstrSPE.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td

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