[PATCH] D137661: [PowerPC] Switch to by-name matching for instructions (part 1 of 2).

[James Y Knight via Phabricator via llvm-commits]

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After https://reviews.llvm.org/D137653 we can now switch the PPC
target away from positional operand matching.

This patch fixes all of the "easy" cases. While this changes a large
number of lines of tablegen source, it results in only a single
non-comment change in the code generated by tablegen: the (unused)
codegen-only "MTVRSAVEv" instruction was previously incorrectly
encoding operand 0, and now encodes (correctly) operand 1.

Changes which result in generated-code changes have been split off
into the next (smaller) patch, for ease of review.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137661

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/lib/Target/PowerPC/PPCInstrFormats.td
  llvm/lib/Target/PowerPC/PPCInstrHTM.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrMMA.td
  llvm/lib/Target/PowerPC/PPCInstrP10.td
  llvm/lib/Target/PowerPC/PPCInstrSPE.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td

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