[PATCH] D136722: [AArch64] Extending lowering of 'zext <Y x i8> %x to <Y x i8X>' to use tbl instructions

[NILANJANA BASU via Phabricator via llvm-commits]

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Added more test cases for zext lowering of different vector types


nilanjana_basu added a comment.

Allowed the zext to tbl lowering for all lengths of vectors


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Added Big-Endian checks for the test cases that I missed earlier


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Ran clang-format


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Allowed all element sizes in the destination element that is a multiple of 8


Adding support for ZExt lowering for destination types beyond the existing support for (8|16) x i32

[AArch64] Patch for lowering zext instructions to 'tbl' for (8|16)xi8 -> (8|16)xi32 conversions in D120571 <https://reviews.llvm.org/D120571> is extended to support zext to 'tbl' lowering for Y x i8 to Y x i8X. Any number of vector elements & any destination element type whose size is a multiple of 8 is allowed for this transformation.

Related microbenchmarks can be added by extending D136274 <https://reviews.llvm.org/D136274>

Depends on  D120571 <https://reviews.llvm.org/D120571>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136722

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
  llvm/test/CodeGen/AArch64/zext-to-tbl.ll
  llvm/test/Transforms/CodeGenPrepare/AArch64/zext-to-shuffle.ll

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