[llvm] 1dd0613 - [X86] SkylakeClientModel - fix instregex typo. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-11-08T18:40:23Z
New Revision: 1dd0613810ff0dd197b50488512d5b58b0020292

URL: https://github.com/llvm/llvm-project/commit/1dd0613810ff0dd197b50488512d5b58b0020292
DIFF: https://github.com/llvm/llvm-project/commit/1dd0613810ff0dd197b50488512d5b58b0020292.diff

LOG: [X86] SkylakeClientModel - fix instregex typo. NFCI.

The extra '?' is useless as it only makes a single letter optional and we can only match the SI64 pattern anyway (V?)CVT(T?)SS2SIrr has a different scheduler def

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SchedSkylakeClient.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 1e6a27d4bc16..efd9fb55332c 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1149,7 +1149,7 @@ def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
-def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64?rr")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
 
 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
   let Latency = 7;