[PATCH] D136172: [AArch64]SME2 Multi vector Sel Load and Store instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3635-3636
+// SME2 Multi-vector - SVE Select
+class sme2_sel_vector_vg24<bits<2> sz, RegisterOperand vector_ty,
+                           string mnemonic>
+    : I<(outs vector_ty:$Zd),
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Please can you pass in `op0:op1:op2` into this class then use `{0, 1, 0, 0, 0, 0}` and `{?, 0, ?, 0, ?, 0}` accordingly?


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3724-3735
+class sme2_ld_vector_vg4_multi_scalar_scalar<bits<2> msz, bit n,
+                                             RegisterOperand multi_vector_ty,
+                                             RegisterOperand gpr_ty,
+                                             string mnemonic>
+  : sme2_ld_vector_vg24_multi_scalar_scalar<msz, n, multi_vector_ty, gpr_ty,
+                                            mnemonic> {
+   bits<3> Zt;
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I'm going to surprise/annoy you here but there's more going on here than I typically like.  Do you mind not having the vg24 base classes for the LD1/ST1 instructions in this patch and just have the vg2/vg4 classes fully define `Inst`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136172/new/

https://reviews.llvm.org/D136172