[llvm] 471f2cf - [X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rm
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 8 06:36:06 PST 2022
Author: Simon Pilgrim
Date: 2022-11-08T14:35:39Z
New Revision: 471f2cff8d84a2d1375b78c3e3e66e7fead2f1ea
URL: https://github.com/llvm/llvm-project/commit/471f2cff8d84a2d1375b78c3e3e66e7fead2f1ea
DIFF: https://github.com/llvm/llvm-project/commit/471f2cff8d84a2d1375b78c3e3e66e7fead2f1ea.diff
LOG: [X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rm
None of Haswell/Broadwell/Skylake/Icelake treat CVTTSS2SI64rm differently from CVTSS2SI64rm (or the AVX variants)
Confirmed with Agner, uops.info and Intel AoM
Added:
Modified:
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedIceLake.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 01c84048c60ba..296008e897746 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -843,10 +843,8 @@ def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
- "(V?)CVT(T?)SD2SIrr",
- "(V?)CVT(T?)SS2SI64rr",
- "(V?)CVT(T?)SS2SIrr")>;
+def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
+ "(V?)CVT(T?)SS2SI(64)?rr")>;
def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
let Latency = 4;
@@ -1202,11 +1200,8 @@ def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
- "(V?)CVT(T?)SD2SI64rm",
- "(V?)CVT(T?)SD2SIrm",
- "VCVTTSS2SI64rm",
- "(V?)CVTTSS2SIrm")>;
+def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
+ "(V?)CVT(T?)SS2SI(64)?rm")>;
def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
let Latency = 9;
@@ -1254,13 +1249,6 @@ def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
}
def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
-def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
- let Latency = 10;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
-
def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
let Latency = 11;
let NumMicroOps = 1;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index bd4cbe2469693..f860d0b1866ee 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1382,11 +1382,8 @@ def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
- "(V?)CVTSS2SI(64)?rm",
- "(V?)CVTTSD2SI(64)?rm",
- "VCVTTSS2SI64rm",
- "(V?)CVTTSS2SIrm")>;
+def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
+ "(V?)CVT(T?)SS2SI(64)?rm")>;
def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let Latency = 10;
@@ -1484,13 +1481,6 @@ def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
}
def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
-def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
- let Latency = 10;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
-
def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 5;
let NumMicroOps = 5;
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index 331fafa6d2fe3..e9721851a1d7d 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -1427,10 +1427,8 @@ def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
- "(V?)CVTSS2SI64(Z?)rr",
- "(V?)CVTTSS2SI64(Z?)rr",
- "VCVTTSS2USI64Zrr")>;
+def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
+ "VCVT(T?)SS2USI64Zrr")>;
def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> {
let Latency = 7;
@@ -1997,13 +1995,6 @@ def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
"VCVT(T?)PS2UQQZrm(b?)")>;
-def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> {
- let Latency = 12;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
-
def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index e92a5a87c7da6..1e6a27d4bc16b 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1379,10 +1379,8 @@ def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
- "(V?)CVT(T?)SD2SI(64)?rm",
- "VCVTTSS2SI64rm",
- "(V?)CVT(T?)SS2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
+ "(V?)CVT(T?)SS2SI(64)?rm")>;
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 11;
@@ -1416,13 +1414,6 @@ def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
}
def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
-def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
- let Latency = 12;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
-
def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 13;
let NumMicroOps = 3;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 5ee909b49d098..86954e6d70686 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1412,10 +1412,8 @@ def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
- "(V?)CVTSS2SI64(Z?)rr",
- "(V?)CVTTSS2SI64(Z?)rr",
- "VCVTTSS2USI64Zrr")>;
+def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
+ "VCVT(T?)SS2USI64Zrr")>;
def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
let Latency = 7;
@@ -1977,13 +1975,6 @@ def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
"VCVT(T?)PS2UQQZrm(b?)")>;
-def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
- let Latency = 12;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
-
def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 13;
let NumMicroOps = 3;
diff --git a/llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
index 81e765219b8a4..c7b5864b2cbe8 100644
--- a/llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx
-# CHECK-NEXT: 4 10 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 11 5.00 divps %xmm0, %xmm2
# CHECK-NEXT: 2 16 5.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
-# CHECK-NEXT: - 43.00 34.50 50.50 32.00 32.00 8.00 41.50 0.50 3.00
+# CHECK-NEXT: - 43.00 34.50 50.50 32.00 32.00 8.00 40.50 0.50 3.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %rcx
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
-# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
# CHECK-NEXT: - 5.00 1.00 - - - - - - - divps %xmm0, %xmm2
# CHECK-NEXT: - 5.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
index a79a47724f603..907db6f44a9e2 100644
--- a/llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx
-# CHECK-NEXT: 4 10 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 13 7.00 divps %xmm0, %xmm2
# CHECK-NEXT: 2 19 7.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 13 7.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
-# CHECK-NEXT: - 56.00 34.50 50.50 32.00 32.00 8.00 41.50 0.50 3.00
+# CHECK-NEXT: - 56.00 34.50 50.50 32.00 32.00 8.00 40.50 0.50 3.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %rcx
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
-# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
# CHECK-NEXT: - 7.00 1.00 - - - - - - - divps %xmm0, %xmm2
# CHECK-NEXT: - 7.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
# CHECK-NEXT: - 7.00 1.00 - - - - - - - divss %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
index 413041d43454b..1730d67115847 100644
--- a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
-# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -335,7 +335,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
-# CHECK-NEXT: - 24.00 66.17 27.17 32.00 32.00 8.00 36.17 0.50 3.00 - -
+# CHECK-NEXT: - 24.00 65.83 27.83 32.00 32.00 8.00 34.83 0.50 3.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
@@ -370,7 +370,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 1.00 - - - - - - - - cvttss2si %xmm0, %ecx
# CHECK-NEXT: - - 1.33 0.33 - - - 1.33 - - - - cvttss2si %xmm0, %rcx
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - - - cvttss2si (%rax), %ecx
-# CHECK-NEXT: - - 1.33 0.33 0.50 0.50 - 1.33 - - - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - - - cvttss2si (%rax), %rcx
# CHECK-NEXT: - 3.00 1.00 - - - - - - - - - divps %xmm0, %xmm2
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - - - divps (%rax), %xmm2
# CHECK-NEXT: - 3.00 1.00 - - - - - - - - - divss %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
index e25e56ce84184..1c77b2962818f 100644
--- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
-# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
-# CHECK-NEXT: - 24.00 71.33 24.33 32.00 32.00 8.00 33.83 0.50 3.00
+# CHECK-NEXT: - 24.00 71.33 24.33 32.00 32.00 8.00 32.83 0.50 3.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - - 1.50 0.50 - - - - - - cvttss2si %xmm0, %ecx
# CHECK-NEXT: - - 1.50 0.50 - - - 1.00 - - cvttss2si %xmm0, %rcx
# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - - - - cvttss2si (%rax), %ecx
-# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - - - - cvttss2si (%rax), %rcx
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divps %xmm0, %xmm2
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
index 0e691f19268f1..82f6d8d1c71ef 100644
--- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
-# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
-# CHECK-NEXT: - 24.00 65.83 25.83 32.00 32.00 8.00 37.83 0.50 3.00
+# CHECK-NEXT: - 24.00 65.50 26.50 32.00 32.00 8.00 36.50 0.50 3.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
# CHECK-NEXT: - - 1.33 0.33 - - - 1.33 - - cvttss2si %xmm0, %rcx
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
-# CHECK-NEXT: - - 1.33 0.33 0.50 0.50 - 1.33 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divps %xmm0, %xmm2
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2
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