[llvm] d917276 - [AArch64]SME2 Single and Multi vector Shift and Multiply instructions
Caroline Concatto via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 8 04:33:18 PST 2022
Author: Caroline Concatto
Date: 2022-11-08T12:32:48Z
New Revision: d917276cd8e8311df2c11a9263f4dfb760be769f
URL: https://github.com/llvm/llvm-project/commit/d917276cd8e8311df2c11a9263f4dfb760be769f
DIFF: https://github.com/llvm/llvm-project/commit/d917276cd8e8311df2c11a9263f4dfb760be769f.diff
LOG: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions
This patch adds the assembly/disassembly for the following instructions:
SQRSHR (four registers): Multi-vector signed saturating rounding shift right narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right narrow by immediate.
SQRSHRN: Multi-vector signed saturating rounding shift right narrow by immediate and interleave.
SQRSHRU (four registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
SQRSHRUN: Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave.
UQRSHR (four registers): Multi-vector unsigned saturating rounding shift right narrow by immediate
(two registers): Multi-vector unsigned saturating rounding shift right narrow by immediate.
UQRSHRN: Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D136150
Added:
llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s
llvm/test/MC/AArch64/SME2/sqrshr.s
llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s
llvm/test/MC/AArch64/SME2/sqrshrn.s
llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s
llvm/test/MC/AArch64/SME2/sqrshru.s
llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s
llvm/test/MC/AArch64/SME2/sqrshrun.s
llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s
llvm/test/MC/AArch64/SME2/uqrshr.s
llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s
llvm/test/MC/AArch64/SME2/uqrshrn.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index fdb5ff967a45f..cd6e95d4f935b 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -606,6 +606,19 @@ defm MOVA_VG2_MXI2Z : sme2_mova_vec_to_array_vg2_multi<"mova">;
defm MOVA_VG4_MXI4Z : sme2_mova_vec_to_array_vg4_multi<"mova">;
defm MOVA_VG2_2ZMXI : sme2_mova_array_to_vec_vg2_multi<"mova">;
defm MOVA_VG4_4ZMXI : sme2_mova_array_to_vec_vg4_multi<"mova">;
+
+defm SQRSHR_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshr", 0b0, 0b0>;
+defm SQRSHR_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshr", 0b000>;
+
+defm UQRSHR_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"uqrshr", 0b0, 0b1>;
+defm UQRSHR_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshr", 0b001>;
+
+defm SQRSHRU_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshru", 0b1, 0b0>;
+defm SQRSHRU_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshru", 0b010>;
+
+defm SQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrn", 0b100>;
+defm UQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshrn", 0b101>;
+defm SQRSHRUN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrun", 0b110>;
}
let Predicates = [HasSME2, HasSMEI16I64] in {
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index ca35343610751..ecc6e97428cc7 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -3569,3 +3569,58 @@ multiclass sme2_mova_array_to_vec_vg4_multi<string mnemonic> {
MatrixIndexGPR32Op8_11,
sme_elm_idx0_7, "mov", "vgx4">;
}
+
+//===----------------------------------------------------------------------===//
+// SME2 multi-vec saturating shift right narrow
+class sme2_sat_shift_vector_vg2<string mnemonic, bit op, bit u>
+ : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4),
+ mnemonic, "\t$Zd, $Zn, $imm4",
+ "", []>, Sched<[]> {
+ bits<4> imm4;
+ bits<4> Zn;
+ bits<5> Zd;
+ let Inst{31-21} = 0b11000001111;
+ let Inst{20} = op;
+ let Inst{19-16} = imm4;
+ let Inst{15-10} = 0b110101;
+ let Inst{9-6} = Zn;
+ let Inst{5} = u;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sme2_sat_shift_vector_vg2<string mnemonic, bit op, bit u> {
+ def _H : sme2_sat_shift_vector_vg2<mnemonic, op, u>;
+}
+
+class sme2_sat_shift_vector_vg4<bits<2> sz, bits<3> op, ZPRRegOp zpr_ty,
+ RegisterOperand vector_ty, Operand imm_ty,
+ string mnemonic>
+ : I<(outs zpr_ty:$Zd), (ins vector_ty:$Zn, imm_ty:$imm),
+ mnemonic, "\t$Zd, $Zn, $imm",
+ "", []>, Sched<[]> {
+ bits<3> Zn;
+ bits<5> Zd;
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b1;
+ // Inst{20-16} = imm5;
+ let Inst{15-11} = 0b11011;
+ let Inst{10} = op{2};
+ let Inst{9-7} = Zn;
+ let Inst{6-5} = op{1-0};
+ let Inst{4-0} = Zd;
+}
+
+multiclass sme2_sat_shift_vector_vg4<string mnemonic, bits<3> op> {
+ def _B : sme2_sat_shift_vector_vg4<{0,1}, op, ZPR8, ZZZZ_s_mul_r, vecshiftR32,
+ mnemonic>{
+ bits<5> imm;
+ let Inst{20-16} = imm;
+ }
+ def _H : sme2_sat_shift_vector_vg4<{1,?}, op, ZPR16, ZZZZ_d_mul_r, vecshiftR64,
+ mnemonic> {
+ bits<6> imm;
+ let Inst{22} = imm{5};
+ let Inst{20-16} = imm{4-0};
+ }
+}
diff --git a/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s
new file mode 100644
index 0000000000000..5b34001cb4328
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s
@@ -0,0 +1,55 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshr z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sqrshr z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z0.h, {z10.s-z12.s}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshr z0.h, {z10.s-z12.s}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqrshr z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z0.h, {z1.s-z2.s}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqrshr z0.h, {z1.s-z2.s}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshr z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: sqrshr z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z31.h, {z28.s-z29.s}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: sqrshr z31.h, {z28.s-z29.s}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z31.b, {z28.s-z31.s}, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32].
+// CHECK-NEXT: sqrshr z31.b, {z28.s-z31.s}, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sqrshr z23.s, {z12.s-z15.s}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshr z23.s, {z12.s-z15.s}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshr z23.b, {z12.d-z15.d}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrshr z23.b, {z12.d-z15.d}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sqrshr.s b/llvm/test/MC/AArch64/SME2/sqrshr.s
new file mode 100644
index 0000000000000..cd32c94f65344
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshr.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00000000
+// CHECK-INST: sqrshr z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x00,0xd4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d400 <unknown>
+
+sqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01010101
+// CHECK-INST: sqrshr z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x55,0xd5,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5d555 <unknown>
+
+sqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10010111
+// CHECK-INST: sqrshr z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0x97,0xd5,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d597 <unknown>
+
+sqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11011111
+// CHECK-INST: sqrshr z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xdf,0xd7,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efd7df <unknown>
+
+
+sqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00000000
+// CHECK-INST: sqrshr z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x00,0xd8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d800 <unknown>
+
+sqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00010101
+// CHECK-INST: sqrshr z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x15,0xd9,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d915 <unknown>
+
+sqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10010111
+// CHECK-INST: sqrshr z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0x97,0xd9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d997 <unknown>
+
+sqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10011111
+// CHECK-INST: sqrshr z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0x9f,0xdb,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdb9f <unknown>
+
+
+sqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00000000
+// CHECK-INST: sqrshr z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x00,0xd8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d800 <unknown>
+
+sqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00010101
+// CHECK-INST: sqrshr z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x15,0xd9,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d915 <unknown>
+
+sqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10010111
+// CHECK-INST: sqrshr z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0x97,0xd9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d997 <unknown>
+
+sqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10011111
+// CHECK-INST: sqrshr z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0x9f,0xdb,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdb9f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s
new file mode 100644
index 0000000000000..92e629376ebee
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshrn z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sqrshrn z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrn z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqrshrn z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshrn z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: sqrshrn z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sqrshrn z23.s, {z12.s-z15.s}, #24
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshrn z23.s, {z12.s-z15.s}, #24
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sqrshrn.s b/llvm/test/MC/AArch64/SME2/sqrshrn.s
new file mode 100644
index 0000000000000..e0c66bbf5e967
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshrn.s
@@ -0,0 +1,65 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00000000
+// CHECK-INST: sqrshrn z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x00,0xdc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160dc00 <unknown>
+
+sqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00010101
+// CHECK-INST: sqrshrn z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x15,0xdd,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175dd15 <unknown>
+
+sqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10010111
+// CHECK-INST: sqrshrn z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0x97,0xdd,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168dd97 <unknown>
+
+sqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10011111
+// CHECK-INST: sqrshrn z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0x9f,0xdf,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdf9f <unknown>
+
+
+sqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00000000
+// CHECK-INST: sqrshrn z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x00,0xdc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0dc00 <unknown>
+
+sqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00010101
+// CHECK-INST: sqrshrn z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x15,0xdd,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5dd15 <unknown>
+
+sqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10010111
+// CHECK-INST: sqrshrn z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0x97,0xdd,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8dd97 <unknown>
+
+sqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10011111
+// CHECK-INST: sqrshrn z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0x9f,0xdf,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdf9f <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s
new file mode 100644
index 0000000000000..cd50ad8f5effc
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s
@@ -0,0 +1,35 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshru z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sqrshru z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshru z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqrshru z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshru z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshru z31.h, {z28.d-z31.d}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sqrshru z23.s, {z12.s-z15.s}, #24
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshru z23.s, {z12.s-z15.s}, #24
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sqrshru.s b/llvm/test/MC/AArch64/SME2/sqrshru.s
new file mode 100644
index 0000000000000..b42cf5ab31518
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshru.s
@@ -0,0 +1,89 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sqrshru z0.h, {z0.s - z1.s}, #16 // 11000001-11110000-11010100-00000000
+// CHECK-INST: sqrshru z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x00,0xd4,0xf0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f0d400 <unknown>
+
+sqrshru z21.h, {z10.s - z11.s}, #11 // 11000001-11110101-11010101-01010101
+// CHECK-INST: sqrshru z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x55,0xd5,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d555 <unknown>
+
+sqrshru z23.h, {z12.s - z13.s}, #8 // 11000001-11111000-11010101-10010111
+// CHECK-INST: sqrshru z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0x97,0xd5,0xf8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f8d597 <unknown>
+
+sqrshru z31.h, {z30.s - z31.s}, #1 // 11000001-11111111-11010111-11011111
+// CHECK-INST: sqrshru z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xdf,0xd7,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffd7df <unknown>
+
+
+sqrshru z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-01000000
+// CHECK-INST: sqrshru z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x40,0xd8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d840 <unknown>
+
+sqrshru z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-01010101
+// CHECK-INST: sqrshru z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x55,0xd9,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d955 <unknown>
+
+sqrshru z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-11010111
+// CHECK-INST: sqrshru z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0xd7,0xd9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d9d7 <unknown>
+
+sqrshru z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-11011111
+// CHECK-INST: sqrshru z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0xdf,0xdb,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdbdf <unknown>
+
+
+sqrshru z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-01000000
+// CHECK-INST: sqrshru z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x40,0xd8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d840 <unknown>
+
+sqrshru z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-01010101
+// CHECK-INST: sqrshru z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x55,0xd9,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d955 <unknown>
+
+sqrshru z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-11010111
+// CHECK-INST: sqrshru z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0xd7,0xd9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d9d7 <unknown>
+
+sqrshru z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-11011111
+// CHECK-INST: sqrshru z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0xdf,0xdb,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdbdf <unknown>
diff --git a/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s
new file mode 100644
index 0000000000000..ac4408e5a8577
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqrshrun z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sqrshrun z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqrshrun z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqrshrun z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+sqrshrun z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: sqrshrun z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sqrshrun z23.s, {z12.s-z15.s}, #24
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqrshrun z23.s, {z12.s-z15.s}, #24
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sqrshrun.s b/llvm/test/MC/AArch64/SME2/sqrshrun.s
new file mode 100644
index 0000000000000..b64dabd4f647d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sqrshrun.s
@@ -0,0 +1,65 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sqrshrun z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-01000000
+// CHECK-INST: sqrshrun z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x40,0xdc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160dc40 <unknown>
+
+sqrshrun z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-01010101
+// CHECK-INST: sqrshrun z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x55,0xdd,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175dd55 <unknown>
+
+sqrshrun z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-11010111
+// CHECK-INST: sqrshrun z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0xd7,0xdd,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ddd7 <unknown>
+
+sqrshrun z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-11011111
+// CHECK-INST: sqrshrun z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0xdf,0xdf,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdfdf <unknown>
+
+
+sqrshrun z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-01000000
+// CHECK-INST: sqrshrun z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x40,0xdc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0dc40 <unknown>
+
+sqrshrun z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-01010101
+// CHECK-INST: sqrshrun z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x55,0xdd,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5dd55 <unknown>
+
+sqrshrun z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-11010111
+// CHECK-INST: sqrshrun z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0xd7,0xdd,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ddd7 <unknown>
+
+sqrshrun z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-11011111
+// CHECK-INST: sqrshrun z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0xdf,0xdf,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdfdf <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s b/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s
new file mode 100644
index 0000000000000..50c221ee66a6b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s
@@ -0,0 +1,55 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uqrshr z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uqrshr z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z0.h, {z10.s-z12.s}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqrshr z0.h, {z10.s-z12.s}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: uqrshr z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z0.h, {z1.s-z2.s}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uqrshr z0.h, {z1.s-z2.s}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+uqrshr z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: uqrshr z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z31.h, {z28.s-z29.s}, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
+// CHECK-NEXT: uqrshr z31.h, {z28.s-z29.s}, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z31.b, {z28.s-z31.s}, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32].
+// CHECK-NEXT: uqrshr z31.b, {z28.s-z31.s}, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+uqrshr z23.s, {z12.s-z15.s}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqrshr z23.s, {z12.s-z15.s}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshr z23.b, {z12.d-z15.d}, #15
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uqrshr z23.b, {z12.d-z15.d}, #15
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/uqrshr.s b/llvm/test/MC/AArch64/SME2/uqrshr.s
new file mode 100644
index 0000000000000..822b4c90ed68d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uqrshr.s
@@ -0,0 +1,90 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00100000
+// CHECK-INST: uqrshr z0.h, { z0.s, z1.s }, #16
+// CHECK-ENCODING: [0x20,0xd4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d420 <unknown>
+
+uqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01110101
+// CHECK-INST: uqrshr z21.h, { z10.s, z11.s }, #11
+// CHECK-ENCODING: [0x75,0xd5,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5d575 <unknown>
+
+uqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10110111
+// CHECK-INST: uqrshr z23.h, { z12.s, z13.s }, #8
+// CHECK-ENCODING: [0xb7,0xd5,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d5b7 <unknown>
+
+uqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11111111
+// CHECK-INST: uqrshr z31.h, { z30.s, z31.s }, #1
+// CHECK-ENCODING: [0xff,0xd7,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efd7ff <unknown>
+
+
+uqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00100000
+// CHECK-INST: uqrshr z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x20,0xd8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d820 <unknown>
+
+uqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00110101
+// CHECK-INST: uqrshr z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x35,0xd9,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d935 <unknown>
+
+uqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10110111
+// CHECK-INST: uqrshr z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0xb7,0xd9,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d9b7 <unknown>
+
+uqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10111111
+// CHECK-INST: uqrshr z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0xbf,0xdb,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdbbf <unknown>
+
+
+uqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00100000
+// CHECK-INST: uqrshr z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x20,0xd8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d820 <unknown>
+
+uqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00110101
+// CHECK-INST: uqrshr z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x35,0xd9,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d935 <unknown>
+
+uqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10110111
+// CHECK-INST: uqrshr z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0xb7,0xd9,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d9b7 <unknown>
+
+uqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10111111
+// CHECK-INST: uqrshr z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0xbf,0xdb,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdbbf <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s
new file mode 100644
index 0000000000000..c3d93ad39e0d7
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uqrshrn z0.b, {z0.s-z4.s}, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uqrshrn z0.b, {z0.s-z4.s}, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqrshrn z0.h, {z1.d-z4.d}, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: uqrshrn z0.h, {z1.d-z4.d}, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate
+
+uqrshrn z31.h, {z28.d-z31.d}, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
+// CHECK-NEXT: uqrshrn z31.h, {z28.d-z31.d}, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+uqrshrn z23.s, {z12.s-z15.s}, #24
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqrshrn z23.s, {z12.s-z15.s}, #24
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/uqrshrn.s b/llvm/test/MC/AArch64/SME2/uqrshrn.s
new file mode 100644
index 0000000000000..a09907fd32341
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uqrshrn.s
@@ -0,0 +1,65 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2 - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00100000
+// CHECK-INST: uqrshrn z0.b, { z0.s - z3.s }, #32
+// CHECK-ENCODING: [0x20,0xdc,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160dc20 <unknown>
+
+uqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00110101
+// CHECK-INST: uqrshrn z21.b, { z8.s - z11.s }, #11
+// CHECK-ENCODING: [0x35,0xdd,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175dd35 <unknown>
+
+uqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10110111
+// CHECK-INST: uqrshrn z23.b, { z12.s - z15.s }, #24
+// CHECK-ENCODING: [0xb7,0xdd,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ddb7 <unknown>
+
+uqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10111111
+// CHECK-INST: uqrshrn z31.b, { z28.s - z31.s }, #1
+// CHECK-ENCODING: [0xbf,0xdf,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fdfbf <unknown>
+
+
+uqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00100000
+// CHECK-INST: uqrshrn z0.h, { z0.d - z3.d }, #64
+// CHECK-ENCODING: [0x20,0xdc,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0dc20 <unknown>
+
+uqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00110101
+// CHECK-INST: uqrshrn z21.h, { z8.d - z11.d }, #11
+// CHECK-ENCODING: [0x35,0xdd,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5dd35 <unknown>
+
+uqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10110111
+// CHECK-INST: uqrshrn z23.h, { z12.d - z15.d }, #24
+// CHECK-ENCODING: [0xb7,0xdd,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ddb7 <unknown>
+
+uqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10111111
+// CHECK-INST: uqrshrn z31.h, { z28.d - z31.d }, #1
+// CHECK-ENCODING: [0xbf,0xdf,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffdfbf <unknown>
+
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