[PATCH] D137623: [Hexagon] Use default attributes for intrinsics

[Nikita Popov via Phabricator via llvm-commits]

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This switches Hexagon intrinsics to use the default attributes (nosync, nofree, nocallback and willreturn). Especially willreturn is needed to prevent optimization regressions in the future.

The only intrinsics I've excluded here are the load/store locked intrinsics, which presumably aren't nosync.


https://reviews.llvm.org/D137623

Files:
  llvm/include/llvm/IR/IntrinsicsHexagon.td
  llvm/test/CodeGen/Hexagon/circ-load-isel.ll
  llvm/test/CodeGen/Hexagon/select-vector-pred.ll


Index: llvm/test/CodeGen/Hexagon/select-vector-pred.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/select-vector-pred.ll
+++ llvm/test/CodeGen/Hexagon/select-vector-pred.ll
@@ -21,8 +21,8 @@
   %3 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %.sroa.speculated.i13.i.i) #3
   %4 = tail call <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1> undef, <128 x i1> %3) #3
   tail call void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1> %4, i8* nonnull undef, <32 x i32> undef) #3
-  unreachable
-                  }
+  ret void
+}
 
 attributes #0 = { nounwind writeonly }
 attributes #1 = { nounwind readnone }
Index: llvm/test/CodeGen/Hexagon/circ-load-isel.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/circ-load-isel.ll
+++ llvm/test/CodeGen/Hexagon/circ-load-isel.ll
@@ -10,7 +10,7 @@
 entry:
   store i32 0, i32* @l, align 4
   %0 = tail call i8* @llvm.hexagon.circ.ldw(i8* undef, i8* undef, i32 150995968, i32 4)
-  unreachable
+  ret void
 }
 
 declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) #1
Index: llvm/include/llvm/IR/IntrinsicsHexagon.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsHexagon.td
+++ llvm/include/llvm/IR/IntrinsicsHexagon.td
@@ -19,14 +19,14 @@
                               list<LLVMType> param_types,
                               list<IntrinsicProperty> properties>
     : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
-      Intrinsic<ret_types, param_types, properties>;
+      DefaultAttrsIntrinsic<ret_types, param_types, properties>;
 
   /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
   /// intrinsics.
   class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
                                  list<LLVMType> param_types,
                                  list<IntrinsicProperty> properties>
-    : Intrinsic<ret_types, param_types, properties>;
+    : DefaultAttrsIntrinsic<ret_types, param_types, properties>;
 }
 
 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
@@ -129,19 +129,27 @@
 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
 
 // Mark locked loads as read/write to prevent any accidental reordering.
-def int_hexagon_L2_loadw_locked :
-Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
-      [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-def int_hexagon_L4_loadd_locked :
-Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
-      [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-
-def int_hexagon_S2_storew_locked :
-Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
-      [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-def int_hexagon_S4_stored_locked :
-Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
-      [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+// These don't use Hexagon_Intrinsic, because they are not nosync, and as such
+// cannot use default attributes.
+let TargetPrefix = "hexagon" in {
+  def int_hexagon_L2_loadw_locked :
+  ClangBuiltin<"__builtin_HEXAGON_L2_loadw_locked">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr32_ty],
+        [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+  def int_hexagon_L4_loadd_locked :
+  ClangBuiltin<"__builtin__HEXAGON_L4_loadd_locked">,
+  Intrinsic<[llvm_i64_ty], [llvm_ptr64_ty],
+        [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+
+  def int_hexagon_S2_storew_locked :
+  ClangBuiltin<"__builtin_HEXAGON_S2_storew_locked">,
+  Intrinsic<[llvm_i32_ty],
+        [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+  def int_hexagon_S4_stored_locked :
+  ClangBuiltin<"__builtin_HEXAGON_S4_stored_locked">,
+  Intrinsic<[llvm_i32_ty],
+        [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+}
 
 def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
     [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],


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