[llvm] 1c35535 - [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m
Haohai Wen via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 7 23:16:58 PST 2022
Author: Haohai Wen
Date: 2022-11-08T15:16:35+08:00
New Revision: 1c355352c73050881f68b3e2b673dc1c7919b67d
URL: https://github.com/llvm/llvm-project/commit/1c355352c73050881f68b3e2b673dc1c7919b67d
DIFF: https://github.com/llvm/llvm-project/commit/1c355352c73050881f68b3e2b673dc1c7919b67d.diff
LOG: [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m
These two instructions are only encodable in 64bit mode.
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D137608
Added:
Modified:
llvm/lib/Target/X86/X86InstrCompiler.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index ab3abe8faca7c..09e31988e5bd8 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -801,9 +801,9 @@ def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs),
return hasNoCarryFlagUses(SDValue(N, 0));
}]>;
-let Predicates = [UseIncDec] in {
- let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
- SchedRW = [WriteALURMW] in {
+let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
+ SchedRW = [WriteALURMW] in {
+ let Predicates = [UseIncDec] in {
def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
"inc{b}\t$dst",
[(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>,
@@ -816,10 +816,6 @@ let Predicates = [UseIncDec] in {
"inc{l}\t$dst",
[(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>,
OpSize32, LOCK;
- def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
- "inc{q}\t$dst",
- [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>,
- LOCK;
def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
"dec{b}\t$dst",
@@ -833,20 +829,33 @@ let Predicates = [UseIncDec] in {
"dec{l}\t$dst",
[(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>,
OpSize32, LOCK;
+ }
+
+ let Predicates = [UseIncDec, In64BitMode] in {
+ def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
+ "inc{q}\t$dst",
+ [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>,
+ LOCK;
def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
"dec{q}\t$dst",
[(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>,
LOCK;
}
+}
+let Predicates = [UseIncDec] in {
// Additional patterns for -1 constant.
def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>;
def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>;
def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>;
- def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>;
def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>;
def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>;
def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>;
+}
+
+let Predicates = [UseIncDec, In64BitMode] in {
+ // Additional patterns for -1 constant.
+ def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>;
def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>;
}
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