[PATCH] D137612: [PowerPC] add a new subtarget feature CheapMFLR

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: RolandF, PowerPC.
Herald added subscribers: kbarton, hiraditya, nemanjai.
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This is to address code review comments in https://reviews.llvm.org/D137423#3912332

Add a new subtarget feature `CheapMFLR`, so that we don't reply on ISA version to check a processor level feature.

This caller of this new feature is in D137423 <https://reviews.llvm.org/D137423> and the tests are also there.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137612

Files:
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h


Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -168,6 +168,7 @@
   bool UsePPCPostRASchedStrategy;
   bool PairedVectorMemops;
   bool PredictableSelectIsExpensive;
+  bool CheapMFLR;
   bool HasModernAIXAs;
   bool IsAIX;
 
@@ -437,6 +438,10 @@
     return PredictableSelectIsExpensive;
   }
 
+  bool isCheapMFLR() const {
+    return CheapMFLR;
+  }
+
   // Select allocation orders of GPRC and G8RC. It should be strictly consistent
   // with corresponding AltOrders in PPCRegisterInfo.td.
   unsigned getGPRAllocationOrderIdx() const {
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -149,6 +149,7 @@
   UsePPCPostRASchedStrategy = false;
   PairedVectorMemops = false;
   PredictableSelectIsExpensive = false;
+  CheapMFLR = false;
   HasModernAIXAs = false;
   IsAIX = false;
 
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -316,6 +316,9 @@
                    "true",
                    "Prefer likely predicted branches over selects">;
 
+def FeatureCheapMFLR :
+  SubtargetFeature<"cheap-MFLR", "CheapMFLR", "true", "Enable cheap MFLR">;
+
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
@@ -424,7 +427,7 @@
     !listconcat(FusionFeatures, [
        DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
        FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
-       FeaturePairedVectorMemops]);
+       FeaturePairedVectorMemops, FeatureCheapMFLR]);
   list<SubtargetFeature> P10SpecificFeatures = [];
   list<SubtargetFeature> P10InheritableFeatures =
     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);


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