[PATCH] D136992: [PowerPC] Add new load/store with length instructions to Future CPU.

[Amy Kwan via Phabricator via llvm-commits]

amyk added a comment.

Thanks for addressing the initial comments that I had. I think aside from these comments I have, the patch LGTM.



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Comment at: llvm/lib/Target/PowerPC/PPCInstrFuture.td:15
+let Predicates = [HasVSX, IsISAFuture] in {
+let mayLoad = 1 in {
+def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
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Another minor nit, but could we:
- Indent the `let mayLoad = 1 in { }` and let `mayStore = 1 in { }` blocks, similar to how in `PPCInstrVSX.td`, we will indent these `mayLoad`/`mayStore` blocks if there are predicates on the outside. 
- Group all loads together in one `mayLoad` block, and stores in one `mayStore` block so that we don't need to add as many of these?


Repository:
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https://reviews.llvm.org/D136992