[PATCH] D137593: [RISCV] Optimize scalable frame setup when VLEN is precisely known

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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If we know the exact value of VLEN, the frame offset adjustment for scalable stack slots becomes a fixed constant.  This avoids the need to read vlenb, and may allow the offset to be folded into the immediate field of an add/sub.

We could go further here, and fold the offset into a single larger frame adjustment - instead of having a separate scalable adjustment step - but that requires a bit more code reorganization.  I may (or may not) return to that in a future patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137593

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll


Index: llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
+++ llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
@@ -87,9 +87,7 @@
 ; SPILL-O2-VLEN128-NEXT:    addi sp, sp, -32
 ; SPILL-O2-VLEN128-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; SPILL-O2-VLEN128-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; SPILL-O2-VLEN128-NEXT:    csrr a1, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a1, a1, 1
-; SPILL-O2-VLEN128-NEXT:    sub sp, sp, a1
+; SPILL-O2-VLEN128-NEXT:    sub sp, sp, 512
 ; SPILL-O2-VLEN128-NEXT:    mv s0, a0
 ; SPILL-O2-VLEN128-NEXT:    addi a1, sp, 16
 ; SPILL-O2-VLEN128-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
@@ -106,9 +104,7 @@
 ; SPILL-O2-VLEN128-NEXT:    addi a0, sp, 16
 ; SPILL-O2-VLEN128-NEXT:    vl1r.v v9, (a0) # Unknown-size Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    vfadd.vv v8, v9, v8
-; SPILL-O2-VLEN128-NEXT:    csrr a0, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a0, a0, 1
-; SPILL-O2-VLEN128-NEXT:    add sp, sp, a0
+; SPILL-O2-VLEN128-NEXT:    add sp, sp, 512
 ; SPILL-O2-VLEN128-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; SPILL-O2-VLEN128-NEXT:    addi sp, sp, 32
Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -379,6 +379,35 @@
     Amount = -Amount;
     Opc = RISCV::SUB;
   }
+
+  // Optimize compile time offset case
+  if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
+    // 1. Multiply the number of v-slots by the (constant) length of register
+    Register ScratchReg =
+      MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+    const int64_t VLENB = STI.getRealMinVLen() / 8;
+    const int64_t Offset = Amount * VLENB;
+    if (!isInt<32>(Offset)) {
+      report_fatal_error(
+        "Frame size outside of the signed 32-bit range not supported");
+    }
+    if (isInt<12>(Offset)) {
+      BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
+        .addReg(SPReg)
+        .addImm(Offset)
+        .setMIFlag(Flag);
+      return;
+    }
+
+    TII->movImm(MBB, MBBI, DL, ScratchReg, Offset);
+    // 2. SP = SP - RVV stack size
+    BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
+        .addReg(SPReg)
+        .addReg(ScratchReg, RegState::Kill)
+        .setMIFlag(Flag);
+    return;
+  }
+
   // 1. Multiply the number of v-slots to the length of registers
   Register FactorRegister =
       MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);


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