[PATCH] D137568: [AArch64][SVE2] Add the SVE2.1 dupq and extq instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

One request but otherwise looks good.



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:9296
+  let Inst{31-21} = 0b00000101001;
+  let Inst{19-16} = tsz;
+  let Inst{15-10} = 0b001001;
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Please can this be 5-bit to cover `20-16` so there's no hole in the instruction. The current name works for me but if you want to change it then that's fine also.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:9303-9304
+multiclass sve2p1_dupq<string mnemonic> {
+  def _B : sve2p1_dupq<{?, ?, ?, 1}, mnemonic, ZPR8, VectorIndexB32b> {
+    bits<4> index;
+    let Inst{20-17} = index;
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FYI: This is what prompted my previous comment.  I know there's no bug here but it just looks wrong index being 4-bit and yet we only passing in 3 `?` to the instruction class.


Repository:
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  https://reviews.llvm.org/D137568/new/

https://reviews.llvm.org/D137568