[PATCH] D134423: [AMDGPU] Fix vgpr2sgpr copy analysis to check scalar operands of buffer instructions use scalar registers.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Without additional context these should be using waterfall loops, not readfirstlane



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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:105
+  // Flag to check if MUBUF/MTBUF needs scalar register.
+  bool HasMBUFScalarReg = false;
   // Count of another VGPR to SGPR copies that contribute to the
----------------
This isn't really specific to MUBUF instructions; it's any operand that has to be scalar. We have to waterfall calls as well


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:918
+          if (Reg.isVirtual() &&
+              (MRI->getRegClass(Reg) == &AMDGPU::SGPR_128RegClass ||
+               MRI->getRegClass(Reg) == &AMDGPU::SReg_32RegClass) &&
----------------
Avoid calling getRegClass multiple times 


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:920
+               MRI->getRegClass(Reg) == &AMDGPU::SReg_32RegClass) &&
+              (TII->isMUBUF(Opc) || TII->isMTBUF(Opc))) {
+            Info.HasMBUFScalarReg = true;
----------------
The MUBUF/MTBUF part isn't interesting, it's the operand being an SGPR and not trivially rewritable as vector 


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https://reviews.llvm.org/D134423