[llvm] a9d7b18 - [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 7 07:51:21 PST 2022
Author: David Sherwood
Date: 2022-11-07T15:51:09Z
New Revision: a9d7b18b4a853daa8fecb5d5863af211841de762
URL: https://github.com/llvm/llvm-project/commit/a9d7b18b4a853daa8fecb5d5863af211841de762
DIFF: https://github.com/llvm/llvm-project/commit/a9d7b18b4a853daa8fecb5d5863af211841de762.diff
LOG: [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d
This patch adds the assembly/disassembly for the following instructions:
st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137245
Added:
llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/ld1d_q.s
llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/ld1w_q.s
llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/st1d_q.s
llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/st1w_q.s
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 2a60c32edc9d..32bdf17a4c3e 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -904,10 +904,16 @@ let Predicates = [HasSVEorSME] in {
defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;
defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
+ let Predicates = [HasSVE2p1] in {
+ defm LD1W_Q_IMM : sve_mem_128b_cld_si<0b10, "ld1w">;
+ }
defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
+ let Predicates = [HasSVE2p1] in {
+ defm LD1D_Q_IMM : sve_mem_128b_cld_si<0b11, "ld1d">;
+ }
// LD1R loads (splat scalar to vector)
defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>;
@@ -965,10 +971,16 @@ let Predicates = [HasSVEorSME] in {
defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
+ let Predicates = [HasSVE2p1] in {
+ defm LD1W_Q : sve_mem_128b_cld_ss<0b10, "ld1w", GPR64NoXZRshifted32>;
+ }
defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;
defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
+ let Predicates = [HasSVE2p1] in {
+ defm LD1D_Q : sve_mem_128b_cld_ss<0b11, "ld1d", GPR64NoXZRshifted64>;
+ }
} // End HasSVEorSME
let Predicates = [HasSVE] in {
@@ -1265,7 +1277,13 @@ let Predicates = [HasSVEorSME] in {
defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>;
defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
+ let Predicates = [HasSVE2p1] in {
+ defm ST1W_Q_IMM : sve_mem_cst_si<0b10, 0b00, "st1w", Z_q, ZPR128>;
+ }
defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
+ let Predicates = [HasSVE2p1] in {
+ defm ST1D_Q_IMM : sve_mem_cst_si<0b11, 0b10, "st1d", Z_q, ZPR128>;
+ }
// contiguous store with reg+reg addressing.
defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
@@ -1277,7 +1295,13 @@ let Predicates = [HasSVEorSME] in {
defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
+ let Predicates = [HasSVE2p1] in {
+ defm ST1W_Q : sve_mem_cst_ss<0b1000, "st1w", Z_q, ZPR128, GPR64NoXZRshifted32>;
+ }
defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
+ let Predicates = [HasSVE2p1] in {
+ defm ST1D_Q : sve_mem_cst_ss<0b1110, "st1d", Z_q, ZPR128, GPR64NoXZRshifted64>;
+ }
} // End HasSVEorSME
let Predicates = [HasSVE] in {
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index f91e5243fca4..f9d6abdd5292 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9221,3 +9221,65 @@ multiclass sve_mem_sst_128b_64_unscaled<string mnemonic> {
def : InstAlias<mnemonic # " $Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
}
+
+
+// SVE contiguous load (quadwords, scalar plus immediate)
+class sve_mem_128b_cld_si<bits<2> dtype, string mnemonic>
+ : I<(outs Z_q:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+ mnemonic, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+ "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Rn;
+ bits<3> Pg;
+ bits<4> imm4;
+ let Inst{31-25} = 0b1010010;
+ let Inst{24-23} = dtype;
+ let Inst{22-20} = 0b001;
+ let Inst{19-16} = imm4;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+}
+
+multiclass sve_mem_128b_cld_si<bits<2> dtype, string mnemonic> {
+ def NAME : sve_mem_128b_cld_si<dtype, mnemonic>;
+
+ def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn]",
+ (!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+ def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn]",
+ (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+ def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+ (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+}
+
+
+// SVE contiguous load (quadwords, scalar plus scalar)
+class sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty>
+ : I<(outs Z_q:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm),
+ mnemonic, "\t$Zt, $Pg/z, [$Rn, $Rm]", "",
+ []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Rn;
+ bits<3> Pg;
+ bits<5> Rm;
+ let Inst{31-25} = 0b1010010;
+ let Inst{24-23} = dtype;
+ let Inst{22-21} = 0b00;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b100;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+}
+
+multiclass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty> {
+ def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>;
+
+ def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]",
+ (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s
new file mode 100644
index 000000000000..7860d9a610d0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s
@@ -0,0 +1,32 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+ld1d {z0.q}, p8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1d {z0.q}, p8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1d {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1d {z0.q}, p0/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d {z0.q}, p0/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d {z3.q}, p0/z, [x0, #8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d {z3.q}, p0/z, [x0, #8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1d_q.s b/llvm/test/MC/AArch64/SVE2p1/ld1d_q.s
new file mode 100644
index 000000000000..12ecde8dc80f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1d_q.s
@@ -0,0 +1,73 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1d {z0.q}, p0/z, [x0, x0, lsl #3] // 10100101-10000000-10000000-00000000
+// CHECK-INST: ld1d { z0.q }, p0/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x80,0x80,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5808000 <unknown>
+
+ld1d {z21.q}, p5/z, [x10, x21, lsl #3] // 10100101-10010101-10010101-01010101
+// CHECK-INST: ld1d { z21.q }, p5/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0x95,0x95,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5959555 <unknown>
+
+ld1d {z23.q}, p3/z, [x13, x8, lsl #3] // 10100101-10001000-10001101-10110111
+// CHECK-INST: ld1d { z23.q }, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x8d,0x88,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5888db7 <unknown>
+
+ld1d z23.q, p3/z, [x13, x8, lsl #3] // 10100101-10001000-10001101-10110111
+// CHECK-INST: ld1d { z23.q }, p3/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x8d,0x88,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5888db7 <unknown>
+
+ld1d {z0.q}, p0/z, [x0] // 10100101-10010000-00100000-00000000
+// CHECK-INST: ld1d { z0.q }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x90,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5902000 <unknown>
+
+ld1d z0.q, p0/z, [x0] // 10100101-10010000-00100000-00000000
+// CHECK-INST: ld1d { z0.q }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x90,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5902000 <unknown>
+
+ld1d {z21.q}, p5/z, [x10, #5, mul vl] // 10100101-10010101-00110101-01010101
+// CHECK-INST: ld1d { z21.q }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0x35,0x95,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5953555 <unknown>
+
+ld1d {z23.q}, p3/z, [x13, #-8, mul vl] // 10100101-10011000-00101101-10110111
+// CHECK-INST: ld1d { z23.q }, p3/z, [x13, #-8, mul vl]
+// CHECK-ENCODING: [0xb7,0x2d,0x98,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5982db7 <unknown>
+
+ld1d {z31.q}, p7/z, [sp, #-1, mul vl] // 10100101-10011111-00111111-11111111
+// CHECK-INST: ld1d { z31.q }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a59f3fff <unknown>
+
+ld1d z31.q, p7/z, [sp, #-1, mul vl] // 10100101-10011111-00111111-11111111
+// CHECK-INST: ld1d { z31.q }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a59f3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s
new file mode 100644
index 000000000000..f049add93eb7
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s
@@ -0,0 +1,32 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+ld1w {z0.q}, p8/z, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1w {z0.q}, p8/z, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1w {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1w {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+ld1w {z0.q}, p0/z, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w {z0.q}, p0/z, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w {z3.q}, p0/z, [x0, #8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w {z3.q}, p0/z, [x0, #8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1w_q.s b/llvm/test/MC/AArch64/SVE2p1/ld1w_q.s
new file mode 100644
index 000000000000..9450ac5b0fe9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1w_q.s
@@ -0,0 +1,62 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1w {z0.q}, p0/z, [x0, x0, lsl #2] // 10100101-00000000-10000000-00000000
+// CHECK-INST: ld1w { z0.q }, p0/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x80,0x00,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5008000 <unknown>
+
+ld1w {z21.q}, p5/z, [x10, x21, lsl #2] // 10100101-00010101-10010101-01010101
+// CHECK-INST: ld1w { z21.q }, p5/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x95,0x15,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5159555 <unknown>
+
+ld1w {z23.q}, p3/z, [x13, x8, lsl #2] // 10100101-00001000-10001101-10110111
+// CHECK-INST: ld1w { z23.q }, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x8d,0x08,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5088db7 <unknown>
+
+ld1w z23.q, p3/z, [x13, x8, lsl #2] // 10100101-00001000-10001101-10110111
+// CHECK-INST: ld1w { z23.q }, p3/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x8d,0x08,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5088db7 <unknown>
+
+ld1w {z0.q}, p0/z, [x0] // 10100101-00010000-00100000-00000000
+// CHECK-INST: ld1w { z0.q }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x10,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5102000 <unknown>
+
+ld1w {z21.q}, p5/z, [x10, #5, mul vl] // 10100101-00010101-00110101-01010101
+// CHECK-INST: ld1w { z21.q }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5153555 <unknown>
+
+ld1w {z23.q}, p3/z, [x13, #-8, mul vl] // 10100101-00011000-00101101-10110111
+// CHECK-INST: ld1w { z23.q }, p3/z, [x13, #-8, mul vl]
+// CHECK-ENCODING: [0xb7,0x2d,0x18,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a5182db7 <unknown>
+
+ld1w {z31.q}, p7/z, [sp, #-1, mul vl] // 10100101-00011111-00111111-11111111
+// CHECK-INST: ld1w { z31.q }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xa5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: a51f3fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s
new file mode 100644
index 000000000000..4ad52197095d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s
@@ -0,0 +1,33 @@
+-26
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+st1d {z0.q}, p8, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1d {z0.q}, p8, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1d {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1d {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+st1d {z0.q}, p0, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: st1d {z0.q}, p0, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d {z3.q}, p0, [x0, #8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: st1d {z3.q}, p0, [x0, #8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1d_q.s b/llvm/test/MC/AArch64/SVE2p1/st1d_q.s
new file mode 100644
index 000000000000..52d1f1635bf3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1d_q.s
@@ -0,0 +1,74 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1d {z0.q}, p0, [x0, x0, lsl #3] // 11100101-11000000-01000000-00000000
+// CHECK-INST: st1d { z0.q }, p0, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c04000 <unknown>
+
+st1d {z21.q}, p5, [x10, x21, lsl #3] // 11100101-11010101-01010101-01010101
+// CHECK-INST: st1d { z21.q }, p5, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5d55555 <unknown>
+
+st1d {z23.q}, p3, [x13, x8, lsl #3] // 11100101-11001000-01001101-10110111
+// CHECK-INST: st1d { z23.q }, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x4d,0xc8,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c84db7 <unknown>
+
+st1d z23.q, p3, [x13, x8, lsl #3] // 11100101-11001000-01001101-10110111
+// CHECK-INST: st1d { z23.q }, p3, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x4d,0xc8,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c84db7 <unknown>
+
+st1d {z0.q}, p0, [x0] // 11100101-11000000-11100000-00000000
+// CHECK-INST: st1d { z0.q }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c0e000 <unknown>
+
+st1d z0.q, p0, [x0] // 11100101-11000000-11100000-00000000
+// CHECK-INST: st1d { z0.q }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c0e000 <unknown>
+
+st1d {z21.q}, p5, [x10, #5, mul vl] // 11100101-11000101-11110101-01010101
+// CHECK-INST: st1d { z21.q }, p5, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xc5,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c5f555 <unknown>
+
+st1d {z23.q}, p3, [x13, #-8, mul vl] // 11100101-11001000-11101101-10110111
+// CHECK-INST: st1d { z23.q }, p3, [x13, #-8, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5c8edb7 <unknown>
+
+st1d {z31.q}, p7, [sp, #-1, mul vl] // 11100101-11001111-11111111-11111111
+// CHECK-INST: st1d { z31.q }, p7, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xff,0xcf,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5cfffff <unknown>
+
+st1d z31.q, p7, [sp, #-1, mul vl] // 11100101-11001111-11111111-11111111
+// CHECK-INST: st1d { z31.q }, p7, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xff,0xcf,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5cfffff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s
new file mode 100644
index 000000000000..d337e6266636
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s
@@ -0,0 +1,32 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+st1w {z0.q}, p8, [x0, x0, lsl #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1w {z0.q}, p8, [x0, x0, lsl #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1w {z23.q}, p2/m, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1w {z23.q}, p2.q, [x13, #-8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid immediate range
+
+st1w {z0.q}, p0, [x0, #-9, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: st1w {z0.q}, p0, [x0, #-9, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w {z3.q}, p0, [x0, #8, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: st1w {z3.q}, p0, [x0, #8, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1w_q.s b/llvm/test/MC/AArch64/SVE2p1/st1w_q.s
new file mode 100644
index 000000000000..efb682692224
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1w_q.s
@@ -0,0 +1,74 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1w {z0.q}, p0, [x0, x0, lsl #2] // 11100101-00000000-01000000-00000000
+// CHECK-INST: st1w { z0.q }, p0, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5004000 <unknown>
+
+st1w {z21.q}, p5, [x10, x21, lsl #2] // 11100101-00010101-01010101-01010101
+// CHECK-INST: st1w { z21.q }, p5, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5155555 <unknown>
+
+st1w {z23.q}, p3, [x13, x8, lsl #2] // 11100101-00001000-01001101-10110111
+// CHECK-INST: st1w { z23.q }, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x08,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5084db7 <unknown>
+
+st1w z23.q, p3, [x13, x8, lsl #2] // 11100101-00001000-01001101-10110111
+// CHECK-INST: st1w { z23.q }, p3, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x08,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e5084db7 <unknown>
+
+st1w {z0.q}, p0, [x0] // 11100101-00000000-11100000-00000000
+// CHECK-INST: st1w { z0.q }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x00,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e500e000 <unknown>
+
+st1w z0.q, p0, [x0] // 11100101-00000000-11100000-00000000
+// CHECK-INST: st1w { z0.q }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x00,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e500e000 <unknown>
+
+st1w {z21.q}, p5, [x10, #5, mul vl] // 11100101-00000101-11110101-01010101
+// CHECK-INST: st1w { z21.q }, p5, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x05,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e505f555 <unknown>
+
+st1w {z23.q}, p3, [x13, #-8, mul vl] // 11100101-00001000-11101101-10110111
+// CHECK-INST: st1w { z23.q }, p3, [x13, #-8, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x08,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e508edb7 <unknown>
+
+st1w {z31.q}, p7, [sp, #-1, mul vl] // 11100101-00001111-11111111-11111111
+// CHECK-INST: st1w { z31.q }, p7, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xff,0x0f,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e50fffff <unknown>
+
+st1w z31.q, p7, [sp, #-1, mul vl] // 11100101-00001111-11111111-11111111
+// CHECK-INST: st1w { z31.q }, p7, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xff,0x0f,0xe5]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e50fffff <unknown>
+
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