[PATCH] D137554: [AArch64][SVE2] Add the SVE2.1 quadword structured load/store instructions

David Sherwood via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 7 07:37:56 PST 2022


david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1014
   // LD(2|3|4) structured loads with reg+immediate
-  defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b,   "ld2b", simm4s2>;
-  defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b,  "ld3b", simm4s3>;
-  defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4s4>;
-  defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h,   "ld2h", simm4s2>;
-  defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h,  "ld3h", simm4s3>;
-  defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4s4>;
-  defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s,   "ld2w", simm4s2>;
-  defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s,  "ld3w", simm4s3>;
-  defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>;
-  defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d,   "ld2d", simm4s2>;
-  defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d,  "ld3d", simm4s3>;
-  defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
+  defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, 0b0, ZZ_b,   "ld2b", simm4s2>;
+  defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, 0b0, ZZZ_b,  "ld3b", simm4s3>;
----------------
I've tried to reuse the existing class by passing in an extra 'q' parameter, but the sz field changes meaning for quadword ops and in fact becomes nregs.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1438
+  let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+  defm ST2Q_IMM : sve_mem_128b_est_si<0b01, ZZ_q,    "st2q", simm4s2>;
+  defm ST3Q_IMM : sve_mem_128b_est_si<0b10, ZZZ_q,   "st3q", simm4s3>;
----------------
It's difficult to reuse the existing sve_mem_est_si and sve_mem_est_ss classes because the sz/nregs fields are shifted, i.e.

sve_mem_est_si:
  let Inst{24-23} = sz;
  let Inst{22-21} = nregs;

sve_mem_128b_est_si:
  let Inst{23-22} = nregs;
  let Inst{21-20} = 0b00;


Repository:
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  https://reviews.llvm.org/D137554/new/

https://reviews.llvm.org/D137554



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