[llvm] cf69895 - [AArch64][SVE2] Add the SVE2.1 BF16 instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 7 07:30:05 PST 2022
Author: David Sherwood
Date: 2022-11-07T15:29:40Z
New Revision: cf69895ab31b40fe0d1275a29c4a29283ce327ae
URL: https://github.com/llvm/llvm-project/commit/cf69895ab31b40fe0d1275a29c4a29283ce327ae
DIFF: https://github.com/llvm/llvm-project/commit/cf69895ab31b40fe0d1275a29c4a29283ce327ae.diff
LOG: [AArch64][SVE2] Add the SVE2.1 BF16 instructions
This patch adds the new FEAT_B16B16 feature as well as the
assembly/disassembly for all of the B16B16 instructions:
bfadd: BFloat16 floating-point add vectors
bfsub: BFloat16 floating-point subtract vectors
bfmul: BFloat16 floating-point multiply vectors
bfclamp: BFloat16 floating-point clamp to minimum/maximum number
bfmax: BFloat16 floating-point maximum
bfmaxnm: BFloat16 floating-point maximum number
bfmin: BFloat16 floating-point minimum
bfminnm: BFloat16 floating-point minimum number
bfmla: BFloat16 floating-point fused multiply-add vectors
bfmls: BFloat16 floating-point fused multiply-subtract vectors
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137321
Added:
llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfadd.s
llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfclamp.s
llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmax.s
llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmin.s
llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfminnm.s
llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmla.s
llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmls.s
llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfmul.s
llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/bfsub.s
Modified:
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index d1366f81cb5b3..e1792a57e35e0 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -129,6 +129,7 @@ AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4",
AARCH64_ARCH_EXT_NAME("sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3")
AARCH64_ARCH_EXT_NAME("sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm", "-sve2-bitperm")
AARCH64_ARCH_EXT_NAME("sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1")
+AARCH64_ARCH_EXT_NAME("b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16")
AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h
index e648ca8aceae0..24ffb9195454a 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -75,6 +75,7 @@ enum ArchExtKind : uint64_t {
AEK_SME2 = 1ULL << 43, // FEAT_SME2
AEK_SVE2p1 = 1ULL << 44, // FEAT_SVE2p1
AEK_SME2p1 = 1ULL << 45, // FEAT_SME2p1
+ AEK_B16B16 = 1ULL << 46 // FEAT_B16B16
};
enum class ArchKind {
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 981e213186bf8..f28f460ea4e72 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -165,6 +165,9 @@ def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "tru
def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
+def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true",
+ "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", []>;
+
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zero-cycle register moves">;
@@ -643,7 +646,7 @@ class AArch64Unsupported { list<Predicate> F; }
def SVEUnsupported : AArch64Unsupported {
let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
- HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME];
+ HasSVE2BitPerm, HasSVEorSME, HasSVE2p1, HasSVE2orSME, HasSVE2p1_or_HasSME2p1];
}
def PAUnsupported : AArch64Unsupported {
@@ -651,7 +654,7 @@ def PAUnsupported : AArch64Unsupported {
}
def SMEUnsupported : AArch64Unsupported {
- let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2, HasSVE2p1_or_HasSME2];
+ let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1];
}
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0439de8c1c190..b3db70967f14e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -138,6 +138,8 @@ def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">;
def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2BitPerm), "sve2-bitperm">;
+def HasB16B16 : Predicate<"Subtarget->hasB16B16()">,
+ AssemblerPredicateWithAll<(all_of FeatureB16B16), "b16b16">;
def HasSME : Predicate<"Subtarget->hasSME()">,
AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;
def HasSMEF64F64 : Predicate<"Subtarget->hasSMEF64F64()">,
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 1549295a72bc4..2a60c32edc9d7 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -689,8 +689,8 @@ let Predicates = [HasSVE] in {
} // End HasSVE
let Predicates = [HasSVEorSME] in {
- defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b0, "fmla", int_aarch64_sve_fmla_lane>;
- defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b1, "fmls", int_aarch64_sve_fmls_lane>;
+ defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b00, "fmla", int_aarch64_sve_fmla_lane>;
+ defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b01, "fmls", int_aarch64_sve_fmls_lane>;
defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla", int_aarch64_sve_fcmla_lane>;
defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul", int_aarch64_sve_fmul_lane>;
@@ -3696,3 +3696,31 @@ defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
} // End HasSVE2p1_or_HasSME2
+
+//===----------------------------------------------------------------------===//
+// SVE2.1 non-widening BFloat16 to BFloat16 instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in {
+def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>;
+def BFSUB_ZZZ : sve_fp_3op_u_zd<0b00, 0b001, "bfsub", ZPR16>;
+def BFMUL_ZZZ : sve_fp_3op_u_zd<0b00, 0b010, "bfmul", ZPR16>;
+
+def BFMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b00, "bfmla", ZPR16>;
+def BFMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b01, "bfmls", ZPR16>;
+
+def BFADD_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0000, "bfadd", ZPR16>;
+def BFSUB_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0001, "bfsub", ZPR16>;
+def BFMUL_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0010, "bfmul", ZPR16>;
+def BFMAXNM_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0100, "bfmaxnm", ZPR16>;
+def BFMINNM_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0101, "bfminnm", ZPR16>;
+def BFMAX_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0110, "bfmax", ZPR16>;
+def BFMIN_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0111, "bfmin", ZPR16>;
+
+defm BFMLA_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmla", 0b10>;
+defm BFMLS_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmls", 0b11>;
+
+defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul">;
+
+def BFCLAMP_ZZZ : sve2p1_fclamp<"bfclamp", 0b00, ZPR16>;
+} // End HasSVE2p1_or_HasSME2p1, HasB16B16
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index c472de8df2f8d..21a0e927d7567 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -18,7 +18,8 @@ def NeoverseN2Model : SchedMachineModel {
let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
let CompleteModel = 1;
- list<Predicate> UnsupportedFeatures = SMEUnsupported.F;
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ [HasSVE2p1]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index e4b2c09ec8d3a..cc6bd90b69568 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3476,6 +3476,7 @@ static const struct Extension {
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
+ {"b16b16", {AArch64::FeatureB16B16}},
{"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}},
{"pauth", {AArch64::FeaturePAuth}},
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 01ef367fef752..f91e5243fca4c 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2105,19 +2105,18 @@ class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
let Constraints = "$Zda = $_Zda";
let ElementSize = zprty.ElementSize;
+ let DestructiveInstType = DestructiveTernaryCommWithRev;
}
multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm, string Ps,
SDPatternOperator op, string revname,
bit isReverseInstr=0> {
- let DestructiveInstType = DestructiveTernaryCommWithRev in {
def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>,
SVEPseudo2Instr<Ps # _H, 1>, SVEInstr2Rev<NAME # _H, revname # _H, isReverseInstr>;
def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>,
SVEPseudo2Instr<Ps # _S, 1>, SVEInstr2Rev<NAME # _S, revname # _S, isReverseInstr>;
def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>,
SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isReverseInstr>;
- }
def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
@@ -2173,7 +2172,7 @@ multiclass sve_fp_3op_p_zds_zx {
// SVE Floating Point Multiply-Add - Indexed Group
//===----------------------------------------------------------------------===//
-class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
+class sve_fp_fma_by_indexed_elem<bits<2> sz, bits<2> opc, string asm,
ZPRRegOp zprty1,
ZPRRegOp zprty2, Operand itype>
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
@@ -2183,8 +2182,8 @@ class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
let Inst{31-24} = 0b01100100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
- let Inst{15-11} = 0;
- let Inst{10} = opc;
+ let Inst{15-12} = 0b0000;
+ let Inst{11-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zda;
@@ -2193,7 +2192,18 @@ class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
let ElementSize = ElementSizeNone;
}
-multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm,
+multiclass sve2p1_fp_bfma_by_indexed_elem<string asm, bits<2> opc> {
+ def NAME : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16,
+ VectorIndexH32b> {
+ bits<3> Zm;
+ bits<3> iop;
+ let Inst{22} = iop{2};
+ let Inst{20-19} = iop{1-0};
+ let Inst{18-16} = Zm;
+ }
+}
+
+multiclass sve_fp_fma_by_indexed_elem<bits<2> opc, string asm,
SDPatternOperator op> {
def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
bits<3> Zm;
@@ -2228,8 +2238,8 @@ multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm,
// SVE Floating Point Multiply - Indexed Group
//===----------------------------------------------------------------------===//
-class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty,
- ZPRRegOp zprty2, Operand itype>
+class sve_fp_fmul_by_indexed_elem<bits<2> sz, bit o2, string asm, ZPRRegOp zprty,
+ ZPRRegOp zprty2, Operand itype>
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop),
asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
bits<5> Zd;
@@ -2237,26 +2247,38 @@ class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty,
let Inst{31-24} = 0b01100100;
let Inst{23-22} = sz;
let Inst{21} = 0b1;
- let Inst{15-10} = 0b001000;
+ let Inst{15-12} = 0b0010;
+ let Inst{11} = o2;
+ let Inst{10} = 0b0;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
}
+multiclass sve2p1_fp_bfmul_by_indexed_elem<string asm> {
+ def NAME : sve_fp_fmul_by_indexed_elem<{0, ?}, 0b1, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
+ bits<3> Zm;
+ bits<3> iop;
+ let Inst{22} = iop{2};
+ let Inst{20-19} = iop{1-0};
+ let Inst{18-16} = Zm;
+ }
+}
+
multiclass sve_fp_fmul_by_indexed_elem<string asm, SDPatternOperator op> {
- def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
+ def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, 0b0, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
bits<3> Zm;
bits<3> iop;
let Inst{22} = iop{2};
let Inst{20-19} = iop{1-0};
let Inst{18-16} = Zm;
}
- def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS32b> {
+ def _S : sve_fp_fmul_by_indexed_elem<0b10, 0b0, asm, ZPR32, ZPR3b32, VectorIndexS32b> {
bits<3> Zm;
bits<2> iop;
let Inst{20-19} = iop;
let Inst{18-16} = Zm;
}
- def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD32b> {
+ def _D : sve_fp_fmul_by_indexed_elem<0b11, 0b0, asm, ZPR64, ZPR4b64, VectorIndexD32b> {
bits<4> Zm;
bit iop;
let Inst{20} = iop;
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s
new file mode 100644
index 0000000000000..1ead9d28277aa
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s
@@ -0,0 +1,36 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfadd z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfadd z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfadd z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfadd z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfadd z23.h, p1/m, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfadd z23.h, p1/m, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfadd z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfadd z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of movprfx
+
+movprfx z23.h, p1/m, z31.h
+bfadd z23.h, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: bfadd z23.h, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfadd.s b/llvm/test/MC/AArch64/SVE2p1/bfadd.s
new file mode 100644
index 0000000000000..1021df12fc050
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfadd.s
@@ -0,0 +1,76 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23.h, p3/m, z31.h
+bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65008db7 <unknown>
+
+movprfx z23, z31
+bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65008db7 <unknown>
+
+bfadd z0.h, p0/m, z0.h, z0.h // 01100101-00000000-10000000-00000000
+// CHECK-INST: bfadd z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65008000 <unknown>
+
+bfadd z21.h, p5/m, z21.h, z10.h // 01100101-00000000-10010101-01010101
+// CHECK-INST: bfadd z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65009555 <unknown>
+
+bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
+// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65008db7 <unknown>
+
+bfadd z31.h, p7/m, z31.h, z31.h // 01100101-00000000-10011111-11111111
+// CHECK-INST: bfadd z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65009fff <unknown>
+
+bfadd z0.h, z0.h, z0.h // 01100101-00000000-00000000-00000000
+// CHECK-INST: bfadd z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x00,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65000000 <unknown>
+
+bfadd z21.h, z10.h, z21.h // 01100101-00010101-00000001-01010101
+// CHECK-INST: bfadd z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x01,0x15,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65150155 <unknown>
+
+bfadd z23.h, z13.h, z8.h // 01100101-00001000-00000001-10110111
+// CHECK-INST: bfadd z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x01,0x08,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 650801b7 <unknown>
+
+bfadd z31.h, z31.h, z31.h // 01100101-00011111-00000011-11111111
+// CHECK-INST: bfadd z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x03,0x1f,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 651f03ff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s
new file mode 100644
index 0000000000000..b18108fcdf08e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfclamp z23.h, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfclamp z23.h, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfclamp z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfclamp z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfclamp.s b/llvm/test/MC/AArch64/SVE2p1/bfclamp.s
new file mode 100644
index 0000000000000..d7b85edb1730e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfclamp.s
@@ -0,0 +1,46 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23, z31
+bfclamp z23.h, z13.h, z8.h // 01100100-00101000-00100101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfclamp z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x25,0x28,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 642825b7 <unknown>
+
+bfclamp z0.h, z0.h, z0.h // 01100100-00100000-00100100-00000000
+// CHECK-INST: bfclamp z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x24,0x20,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64202400 <unknown>
+
+bfclamp z21.h, z10.h, z21.h // 01100100-00110101-00100101-01010101
+// CHECK-INST: bfclamp z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x25,0x35,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64352555 <unknown>
+
+bfclamp z23.h, z13.h, z8.h // 01100100-00101000-00100101-10110111
+// CHECK-INST: bfclamp z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x25,0x28,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 642825b7 <unknown>
+
+bfclamp z31.h, z31.h, z31.h // 01100100-00111111-00100111-11111111
+// CHECK-INST: bfclamp z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x27,0x3f,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 643f27ff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s
new file mode 100644
index 0000000000000..f7e30713e7d52
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfmax z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfmax z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmax z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmax z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmax z23.h, p1/z, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmax z23.h, p1/z, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmax z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmax z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmax.s b/llvm/test/MC/AArch64/SVE2p1/bfmax.s
new file mode 100644
index 0000000000000..cd67abc498f3b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmax.s
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23.h, p3/m, z31.h
+bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65068db7 <unknown>
+
+movprfx z23, z31
+bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65068db7 <unknown>
+
+bfmax z0.h, p0/m, z0.h, z0.h // 01100101-00000110-10000000-00000000
+// CHECK-INST: bfmax z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65068000 <unknown>
+
+bfmax z21.h, p5/m, z21.h, z10.h // 01100101-00000110-10010101-01010101
+// CHECK-INST: bfmax z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65069555 <unknown>
+
+bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
+// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65068db7 <unknown>
+
+bfmax z31.h, p7/m, z31.h, z31.h // 01100101-00000110-10011111-11111111
+// CHECK-INST: bfmax z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x06,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65069fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s
new file mode 100644
index 0000000000000..220b66b435ed4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfmaxnm z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfmaxnm z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmaxnm z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmaxnm z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmaxnm z23.h, p1/z, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmaxnm z23.h, p1/z, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmaxnm z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmaxnm z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s b/llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
new file mode 100644
index 0000000000000..83669ebc42b1f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23.h, p3/m, z31.h
+bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65048db7 <unknown>
+
+movprfx z23, z31
+bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65048db7 <unknown>
+
+bfmaxnm z0.h, p0/m, z0.h, z0.h // 01100101-00000100-10000000-00000000
+// CHECK-INST: bfmaxnm z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65048000 <unknown>
+
+bfmaxnm z21.h, p5/m, z21.h, z10.h // 01100101-00000100-10010101-01010101
+// CHECK-INST: bfmaxnm z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65049555 <unknown>
+
+bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
+// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65048db7 <unknown>
+
+bfmaxnm z31.h, p7/m, z31.h, z31.h // 01100101-00000100-10011111-11111111
+// CHECK-INST: bfmaxnm z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x04,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65049fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s
new file mode 100644
index 0000000000000..a7f8be225fac9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfmin z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfmin z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmin z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmin z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmin z23.h, p1/z, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmin z23.h, p1/z, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmin z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmin z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmin.s b/llvm/test/MC/AArch64/SVE2p1/bfmin.s
new file mode 100644
index 0000000000000..1bb3a0e6f1f26
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmin.s
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23.h, p3/m, z31.h
+bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65078db7 <unknown>
+
+movprfx z23, z31
+bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65078db7 <unknown>
+
+bfmin z0.h, p0/m, z0.h, z0.h // 01100101-00000111-10000000-00000000
+// CHECK-INST: bfmin z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65078000 <unknown>
+
+bfmin z21.h, p5/m, z21.h, z10.h // 01100101-00000111-10010101-01010101
+// CHECK-INST: bfmin z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65079555 <unknown>
+
+bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
+// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65078db7 <unknown>
+
+bfmin z31.h, p7/m, z31.h, z31.h // 01100101-00000111-10011111-11111111
+// CHECK-INST: bfmin z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x07,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65079fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s
new file mode 100644
index 0000000000000..68c4211afa627
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfminnm z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfminnm z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfminnm z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfminnm z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfminnm z23.h, p1/z, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfminnm z23.h, p1/z, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfminnm z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfminnm z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfminnm.s b/llvm/test/MC/AArch64/SVE2p1/bfminnm.s
new file mode 100644
index 0000000000000..9f444c7ac26ae
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfminnm.s
@@ -0,0 +1,54 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23.h, p3/m, z31.h
+bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65058db7 <unknown>
+
+movprfx z23, z31
+bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65058db7 <unknown>
+
+bfminnm z0.h, p0/m, z0.h, z0.h // 01100101-00000101-10000000-00000000
+// CHECK-INST: bfminnm z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65058000 <unknown>
+
+bfminnm z21.h, p5/m, z21.h, z10.h // 01100101-00000101-10010101-01010101
+// CHECK-INST: bfminnm z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65059555 <unknown>
+
+bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
+// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65058db7 <unknown>
+
+bfminnm z31.h, p7/m, z31.h, z31.h // 01100101-00000101-10011111-11111111
+// CHECK-INST: bfminnm z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x05,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65059fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s
new file mode 100644
index 0000000000000..035f2898e2b92
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s
@@ -0,0 +1,41 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmla z0.h, z0.h, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmla z0.h, z0.h, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmla z0.h, z0.h, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmla z0.h, z0.h, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmla z0.h, z0.h, z8.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
+// CHECK-NEXT: bfmla z0.h, z0.h, z8.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmla z0.h, z0.s, z0.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmla z0.h, z0.s, z0.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmla z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmla z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of movprfx
+
+movprfx z23.h, p1/m, z31.h
+bfmla z23.h, z12.h, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: bfmla z23.h, z12.h, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmla.s b/llvm/test/MC/AArch64/SVE2p1/bfmla.s
new file mode 100644
index 0000000000000..ff257830a13da
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmla.s
@@ -0,0 +1,87 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23, z31
+bfmla z23.h, z13.h, z0.h[5] // 01100100-01101000-00001001-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmla z23.h, z13.h, z0.h[5]
+// CHECK-ENCODING: [0xb7,0x09,0x68,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 646809b7 <unknown>
+
+bfmla z0.h, z0.h, z0.h[0] // 01100100-00100000-00001000-00000000
+// CHECK-INST: bfmla z0.h, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x08,0x20,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64200800 <unknown>
+
+bfmla z21.h, z10.h, z5.h[6] // 01100100-01110101-00001001-01010101
+// CHECK-INST: bfmla z21.h, z10.h, z5.h[6]
+// CHECK-ENCODING: [0x55,0x09,0x75,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64750955 <unknown>
+
+bfmla z23.h, z13.h, z0.h[5] // 01100100-01101000-00001001-10110111
+// CHECK-INST: bfmla z23.h, z13.h, z0.h[5]
+// CHECK-ENCODING: [0xb7,0x09,0x68,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 646809b7 <unknown>
+
+bfmla z31.h, z31.h, z7.h[7] // 01100100-01111111-00001011-11111111
+// CHECK-INST: bfmla z31.h, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xff,0x0b,0x7f,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 647f0bff <unknown>
+
+
+movprfx z23.h, p3/m, z31.h
+bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65280db7 <unknown>
+
+movprfx z23, z31
+bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65280db7 <unknown>
+
+bfmla z0.h, p0/m, z0.h, z0.h // 01100101-00100000-00000000-00000000
+// CHECK-INST: bfmla z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x00,0x20,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65200000 <unknown>
+
+bfmla z21.h, p5/m, z10.h, z21.h // 01100101-00110101-00010101-01010101
+// CHECK-INST: bfmla z21.h, p5/m, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x15,0x35,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65351555 <unknown>
+
+bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
+// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65280db7 <unknown>
+
+bfmla z31.h, p7/m, z31.h, z31.h // 01100101-00111111-00011111-11111111
+// CHECK-INST: bfmla z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x1f,0x3f,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 653f1fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s
new file mode 100644
index 0000000000000..cbc7efe9df7aa
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s
@@ -0,0 +1,41 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmls z0.h, z0.h, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmls z0.h, z0.h, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmls z0.h, z0.h, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmls z0.h, z0.h, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmls z0.h, z0.h, z8.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
+// CHECK-NEXT: bfmls z0.h, z0.h, z8.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmls z0.h, z0.s, z0.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmls z0.h, z0.s, z0.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmls z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmls z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of movprfx
+
+movprfx z23.h, p1/m, z31.h
+bfmls z23.h, z12.h, z0.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: bfmls z23.h, z12.h, z0.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmls.s b/llvm/test/MC/AArch64/SVE2p1/bfmls.s
new file mode 100644
index 0000000000000..c153b56b9586b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmls.s
@@ -0,0 +1,87 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+movprfx z23, z31
+bfmls z23.h, z13.h, z0.h[5] // 01100100-01101000-00001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmls z23.h, z13.h, z0.h[5]
+// CHECK-ENCODING: [0xb7,0x0d,0x68,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64680db7 <unknown>
+
+bfmls z0.h, z0.h, z0.h[0] // 01100100-00100000-00001100-00000000
+// CHECK-INST: bfmls z0.h, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x0c,0x20,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64200c00 <unknown>
+
+bfmls z21.h, z10.h, z5.h[6] // 01100100-01110101-00001101-01010101
+// CHECK-INST: bfmls z21.h, z10.h, z5.h[6]
+// CHECK-ENCODING: [0x55,0x0d,0x75,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64750d55 <unknown>
+
+bfmls z23.h, z13.h, z0.h[5] // 01100100-01101000-00001101-10110111
+// CHECK-INST: bfmls z23.h, z13.h, z0.h[5]
+// CHECK-ENCODING: [0xb7,0x0d,0x68,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64680db7 <unknown>
+
+bfmls z31.h, z31.h, z7.h[7] // 01100100-01111111-00001111-11111111
+// CHECK-INST: bfmls z31.h, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xff,0x0f,0x7f,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 647f0fff <unknown>
+
+
+movprfx z23.h, p3/m, z31.h
+bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65282db7 <unknown>
+
+movprfx z23, z31
+bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65282db7 <unknown>
+
+bfmls z0.h, p0/m, z0.h, z0.h // 01100101-00100000-00100000-00000000
+// CHECK-INST: bfmls z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x20,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65202000 <unknown>
+
+bfmls z21.h, p5/m, z10.h, z21.h // 01100101-00110101-00110101-01010101
+// CHECK-INST: bfmls z21.h, p5/m, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x35,0x35,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65353555 <unknown>
+
+bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
+// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65282db7 <unknown>
+
+bfmls z31.h, p7/m, z31.h, z31.h // 01100101-00111111-00111111-11111111
+// CHECK-INST: bfmls z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x3f,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 653f3fff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s
new file mode 100644
index 0000000000000..51adae0689603
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s
@@ -0,0 +1,36 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfmul z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfmul z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmul z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmul z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmul z23.h, p1/m, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmul z23.h, p1/m, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmul z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmul z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of movprfx
+
+movprfx z23.h, p1/m, z31.h
+bfmul z23.h, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: bfmul z23.h, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmul.s b/llvm/test/MC/AArch64/SVE2p1/bfmul.s
new file mode 100644
index 0000000000000..e0b93bcbb1035
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfmul.s
@@ -0,0 +1,101 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+bfmul z0.h, z0.h, z0.h[0] // 01100100-00100000-00101000-00000000
+// CHECK-INST: bfmul z0.h, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x28,0x20,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64202800 <unknown>
+
+bfmul z21.h, z10.h, z5.h[6] // 01100100-01110101-00101001-01010101
+// CHECK-INST: bfmul z21.h, z10.h, z5.h[6]
+// CHECK-ENCODING: [0x55,0x29,0x75,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 64752955 <unknown>
+
+bfmul z23.h, z13.h, z0.h[5] // 01100100-01101000-00101001-10110111
+// CHECK-INST: bfmul z23.h, z13.h, z0.h[5]
+// CHECK-ENCODING: [0xb7,0x29,0x68,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 646829b7 <unknown>
+
+bfmul z31.h, z31.h, z7.h[7] // 01100100-01111111-00101011-11111111
+// CHECK-INST: bfmul z31.h, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xff,0x2b,0x7f,0x64]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 647f2bff <unknown>
+
+movprfx z23.h, p3/m, z31.h
+bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65028db7 <unknown>
+
+movprfx z23, z31
+bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65028db7 <unknown>
+
+bfmul z0.h, p0/m, z0.h, z0.h // 01100101-00000010-10000000-00000000
+// CHECK-INST: bfmul z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65028000 <unknown>
+
+bfmul z21.h, p5/m, z21.h, z10.h // 01100101-00000010-10010101-01010101
+// CHECK-INST: bfmul z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65029555 <unknown>
+
+bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
+// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65028db7 <unknown>
+
+bfmul z31.h, p7/m, z31.h, z31.h // 01100101-00000010-10011111-11111111
+// CHECK-INST: bfmul z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x02,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65029fff <unknown>
+
+bfmul z0.h, z0.h, z0.h // 01100101-00000000-00001000-00000000
+// CHECK-INST: bfmul z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x08,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65000800 <unknown>
+
+bfmul z21.h, z10.h, z21.h // 01100101-00010101-00001001-01010101
+// CHECK-INST: bfmul z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x09,0x15,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65150955 <unknown>
+
+bfmul z23.h, z13.h, z8.h // 01100101-00001000-00001001-10110111
+// CHECK-INST: bfmul z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x09,0x08,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 650809b7 <unknown>
+
+bfmul z31.h, z31.h, z31.h // 01100101-00011111-00001011-11111111
+// CHECK-INST: bfmul z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x0b,0x1f,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 651f0bff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s
new file mode 100644
index 0000000000000..86cb32075f501
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s
@@ -0,0 +1,36 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+bfsub z23.h, p8/m, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: bfsub z23.h, p8/m, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub z23.h, p1/z, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfsub z23.h, p1/z, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfsub z23.h, p1/m, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfsub z23.h, p1/m, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub z23.s, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfsub z23.s, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid use of movprfx
+
+movprfx z23.h, p1/m, z31.h
+bfsub z23.h, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: bfsub z23.h, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/bfsub.s b/llvm/test/MC/AArch64/SVE2p1/bfsub.s
new file mode 100644
index 0000000000000..42cb6772c3a51
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/bfsub.s
@@ -0,0 +1,76 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sve2p1,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | llvm-objdump -d --mattr=-b16b16 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1,+b16b16 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23.h, p3/m, z31.h
+bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
+// CHECK-INST: movprfx z23.h, p3/m, z31.h
+// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65018db7 <unknown>
+
+movprfx z23, z31
+bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
+// CHECK-INST: movprfx z23, z31
+// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65018db7 <unknown>
+
+bfsub z0.h, p0/m, z0.h, z0.h // 01100101-00000001-10000000-00000000
+// CHECK-INST: bfsub z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65018000 <unknown>
+
+bfsub z21.h, p5/m, z21.h, z10.h // 01100101-00000001-10010101-01010101
+// CHECK-INST: bfsub z21.h, p5/m, z21.h, z10.h
+// CHECK-ENCODING: [0x55,0x95,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65019555 <unknown>
+
+bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
+// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65018db7 <unknown>
+
+bfsub z31.h, p7/m, z31.h, z31.h // 01100101-00000001-10011111-11111111
+// CHECK-INST: bfsub z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x9f,0x01,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65019fff <unknown>
+
+bfsub z0.h, z0.h, z0.h // 01100101-00000000-00000100-00000000
+// CHECK-INST: bfsub z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x04,0x00,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65000400 <unknown>
+
+bfsub z21.h, z10.h, z21.h // 01100101-00010101-00000101-01010101
+// CHECK-INST: bfsub z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x05,0x15,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 65150555 <unknown>
+
+bfsub z23.h, z13.h, z8.h // 01100101-00001000-00000101-10110111
+// CHECK-INST: bfsub z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x05,0x08,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 650805b7 <unknown>
+
+bfsub z31.h, z31.h, z31.h // 01100101-00011111-00000111-11111111
+// CHECK-INST: bfsub z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x07,0x1f,0x65]
+// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
+// CHECK-UNKNOWN: 651f07ff <unknown>
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 904a7316c5046..dd4e5fcd0fa22 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1519,7 +1519,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
- AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1};
+ AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
+ AArch64::AEK_B16B16};
std::vector<StringRef> Features;
@@ -1559,6 +1560,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-bitperm"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2p1"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+b16b16"));
EXPECT_TRUE(llvm::is_contained(Features, "+rcpc"));
EXPECT_TRUE(llvm::is_contained(Features, "+rand"));
EXPECT_TRUE(llvm::is_contained(Features, "+mte"));
@@ -1642,6 +1644,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
{"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
{"sve2p1", "nosve2p1", "+sve2p1", "-sve2p1"},
+ {"b16b16", "nob16b16", "+b16b16", "-b16b16"},
{"sve2-bitperm", "nosve2-bitperm", "+sve2-bitperm", "-sve2-bitperm"},
{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"rcpc", "norcpc", "+rcpc", "-rcpc"},
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