[PATCH] D136771: [AArch64] Canonicalize SIGN_EXTEND to VSELECT

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5418
+  if (HandOpcode == ISD::VSELECT &&
+      N0->getOperand(0)->getValueType(0).isScalableVector() &&
+      N0->getOperand(0)->getValueType(0).getScalarType() == MVT::i1 &&
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dmgreen wrote:
> I don't think this is limited to scalable vectors?
indeed - I'd like to see what effect this has on other targets for fixed vectors (where we have a lot more test coverage e.g. AVX512)


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5561
+  EVT VT = Op->getValueType(0);
+  SDValue MinusOnes = DAG.getConstant(APInt(VT.getScalarType().getScalarSizeInBits(), -1, true), DL, VT);
+  SDValue Zeros = DAG.getConstant(APInt(VT.getScalarType().getScalarSizeInBits(), 0, true), DL, VT);
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DAG.getAllOnesConstant ?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18364
+      !ISD::isConstantSplatVector(N->getOperand(1).getNode(), SplatVal) ||
+      SplatVal.getSExtValue() != -1)
+    return false;
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!SplatVal.isAllOnes() 


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Comment at: llvm/test/CodeGen/AArch64/predicated-add-sub-mul.ll:224
 
+define <vscale x 2 x i32> @sext.add2(<vscale x 2 x i32> %a0, <vscale x 2 x i32> %a1) #0 {
+; CHECK-LABEL: sext.add2:
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please can you pre-commit these tests with current (trunk) codegen and then rebase the patch to show the codegen diff


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136771/new/

https://reviews.llvm.org/D136771