[PATCH] D137547: Use ptrue instruction for get_active_lane_mask instrinis if range is from 0 to SVE prdicator constant
Dinar Temirbulatov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 7 05:51:00 PST 2022
dtemirbulatov created this revision.
Herald added subscribers: hiraditya, tschuett.
Herald added a project: All.
dtemirbulatov requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
https://reviews.llvm.org/D137547
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/active_lane_mask.ll
Index: llvm/test/CodeGen/AArch64/active_lane_mask.ll
===================================================================
--- llvm/test/CodeGen/AArch64/active_lane_mask.ll
+++ llvm/test/CodeGen/AArch64/active_lane_mask.ll
@@ -475,6 +475,15 @@
ret <2 x i1> %active.lane.mask
}
+define <vscale x 4 x i1> @lane_mask_nxv4i1_imm() {
+; CHECK-LABEL: lane_mask_nxv4i1_imm:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s, vl6
+; CHECK-NEXT: ret
+entry:
+ %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 6)
+ ret <vscale x 4 x i1> %active.lane.mask
+}
declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17446,6 +17446,13 @@
Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtVT, Res,
DAG.getConstant(0, DL, MVT::i64));
Res = DAG.getNode(ISD::TRUNCATE, DL, VT, Res);
+ } else {
+ if (isa<ConstantSDNode>(N->getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(2)) &&
+ N->getConstantOperandVal(1) == 0 &&
+ getNumElementsFromSVEPredPattern(N->getConstantOperandVal(2)))
+ return getPTrue(DAG, SDLoc(N), N->getValueType(0),
+ N->getConstantOperandVal(2));
}
return Res;
}
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