[PATCH] D136771: [AArch64] Canonicalize SIGN_EXTEND to VSELECT

[Dave Green via Phabricator via llvm-commits]

dmgreen added a reviewer: RKSimon.
dmgreen added a comment.

To add some extra context @NicolaLancellotti wrote this as an extension to D135596 <https://reviews.llvm.org/D135596>. It requires a lot more changes though, and my feeling is that we might be playing whack-a-mole with generic combines that all assume sext's. As we had the patch I suggested putting it up to see what others thought. So.. what do others think?



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5418
+  if (HandOpcode == ISD::VSELECT &&
+      N0->getOperand(0)->getValueType(0).isScalableVector() &&
+      N0->getOperand(0)->getValueType(0).getScalarType() == MVT::i1 &&
----------------
I don't think this is limited to scalable vectors?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5421
+      ISD::isConstantSplatVectorAllZeros(N0->getOperand(2).getNode()) &&
+      ISD::isConstantSplatVector(N0->getOperand(1).getNode(), SplatVal) &&
+      SplatVal.getSExtValue() == -1 &&
----------------
Could this use isConstantSplatVectorAllOnes?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5431
+    // instructions without eliminating anything.
+    if (!N0.hasOneUse() && !N1.hasOneUse())
+      return SDValue();
----------------
Could this be part of the if condition?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136771/new/

https://reviews.llvm.org/D136771