[PATCH] D137419: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:9259
+// SVE floating-point recursive reduction (quadwords)
+class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
+                            RegisterOperand zpr_ty, string vec_sfx>
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paulwalker-arm wrote:
> As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?
I'm not sure what you mean to be honest, given these are not integer reductions and have completely different encoding groups to the integer variants. I can't see much reuse here for example:

SVE floating-point recursive reduction (quadwords): bits 31-24: 0b01100100, bits 21-19: 0b010
SVE bitwise logical reduction (quadwords): bits 31-24: 0b00000100, bits 21-19: 0b011

Is there something about the naming scheme instead that you wish to change?



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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137419/new/

https://reviews.llvm.org/D137419