[PATCH] D137481: [TargetLowering] Do not shrink shift amount in ShrinkDemandedOp

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

This is only called for constant shift amounts. Won't LegalizeDAG fix it if DAG combine changes it after legalization? Have you seen a failure in a larger test?



================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:586
+      SDValue RHS = Op.getOperand(1);
+      // Shift amout type is determined by TLI.getShiftAmountTy,
+      // we can't truncate here because it will cause type mismatch.
----------------
amout->amount


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:588
+      // we can't truncate here because it will cause type mismatch.
+      if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL &&
+          Op.getOpcode() != ISD::SRA)
----------------
This function is never called for SRL or SRA.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137481/new/

https://reviews.llvm.org/D137481