[PATCH] D137450: [RISCV] Support shift/rotate amount operands in isAllUsesReadW.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 4 11:04:17 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: mohammed-nurulhoque, reames, kito-cheng, frasercrmck, asb, luismarques.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
These operands use 6 bits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D137450
Files:
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -139,6 +139,22 @@
Worklist.push_back(UserMI);
break;
+ case RISCV::SLL:
+ // Operand 2 is the shift amount which uses 6 bits.
+ if (OpIdx == 2)
+ break;
+ Worklist.push_back(UserMI);
+ break;
+
+ case RISCV::SRA:
+ case RISCV::SRL:
+ case RISCV::ROL:
+ case RISCV::ROR:
+ // Operand 2 is the shift amount which uses 6 bits.
+ if (OpIdx == 2)
+ break;
+ return false;
+
case RISCV::ADD_UW:
case RISCV::SH1ADD_UW:
case RISCV::SH2ADD_UW:
@@ -172,7 +188,6 @@
case RISCV::AND:
case RISCV::MUL:
case RISCV::OR:
- case RISCV::SLL:
case RISCV::SUB:
case RISCV::XOR:
case RISCV::XORI:
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