[PATCH] D137449: [RISCV] Improve support for ADD_UW/SHXADD_UW in isAllUsesReadW.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: mohammed-nurulhoque, reames, kito-cheng, frasercrmck, asb, luismarques.
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The first use operand of these is implicitly zero extended. We
can consider that a W read. If the use is the other operand, we
need to look through the instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137449

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp


Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -139,6 +139,16 @@
         Worklist.push_back(UserMI);
         break;
 
+      case RISCV::ADD_UW:
+      case RISCV::SH1ADD_UW:
+      case RISCV::SH2ADD_UW:
+      case RISCV::SH3ADD_UW:
+        // Operand 1 is implicitly zero extended.
+        if (OpIdx == 1)
+          break;
+        Worklist.push_back(UserMI);
+        break;
+
       case RISCV::BEXTI:
         if (UserMI->getOperand(2).getImm() >= 32)
           return false;
@@ -167,17 +177,13 @@
       case RISCV::XOR:
       case RISCV::XORI:
 
-      case RISCV::ADD_UW:
       case RISCV::ANDN:
       case RISCV::CLMUL:
       case RISCV::ORC_B:
       case RISCV::ORN:
       case RISCV::SH1ADD:
-      case RISCV::SH1ADD_UW:
       case RISCV::SH2ADD:
-      case RISCV::SH2ADD_UW:
       case RISCV::SH3ADD:
-      case RISCV::SH3ADD_UW:
       case RISCV::XNOR:
         Worklist.push_back(UserMI);
         break;


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