[PATCH] D137411: [AArch64][SVE2] Add the SVE2.1 logical quadword reduction instructions

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 4 07:28:53 PDT 2022


paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3701
+let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+defm ORQV  : sve2p1_log_reduction_q<0b00, "orqv">;
+defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">;
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Please add the usual register suffixes, so `_VPZ` in this case?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:9208
+    : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
+        mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
+        "", []>, Sched<[]> {
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Not your fault but this is a shame because otherwise we could just extend `sve_int_reduce`.

With that said, are you able to follow the same idiom as `sve_int_reduce` for the `QV` reductions because your current direction will mean a separate instruction class per type of reduction and I cannot immediately see a need for that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137411/new/

https://reviews.llvm.org/D137411



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