[PATCH] D137411: [AArch64][SVE2] Add the SVE2.1 logical quadword reduction instructions

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
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This patch adds the assembly/disassembly for the following instructions:

andqv : Bitwise AND reduction of quadword vector segments
eorqv : Bitwise exclusive OR reduction of quadword vector segments
orqv  : Bitwise inclusive OR reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137411

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/andqv.s
  llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/eorqv.s
  llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/orqv.s

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