[PATCH] D136448: [AMDGPU][GISel] Add llvm.amdgcn.icmp selection

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir:28
     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32-NEXT: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
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Joe_Nash wrote:
> Why has the dst class been changed to sreg_32? These instructions should not write to m0 or exec
Dst is constrained to `getBoolRC`. If we want xexec we need to use `getWaveMaskRegClass` instead
Not sure which one is technically correct? Isn't sreg_32 more correct because the dst is always a sgpr, and never exec/m0?


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  https://reviews.llvm.org/D136448/new/

https://reviews.llvm.org/D136448