[PATCH] D136448: [AMDGPU][GISel] Add llvm.amdgcn.icmp selection
Joe Nash via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 3 08:11:10 PDT 2022
Joe_Nash added a comment.
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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir:28
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; WAVE32-NEXT: [[V_CMP_EQ_U16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U16_e64 [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_U16_e64_]]
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Why has the dst class been changed to sreg_32? These instructions should not write to m0 or exec
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https://reviews.llvm.org/D136448/new/
https://reviews.llvm.org/D136448
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