[llvm] 2fb1324 - [RISCV] Add FMV_H_X/FMV_W_X/FCVT_H_W/FCVT_H_WU to isAllUsesReadW in SExtWRemoval.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-03T23:59:09-07:00
New Revision: 2fb1324736f69391636297f973e697c41e2d7a61

URL: https://github.com/llvm/llvm-project/commit/2fb1324736f69391636297f973e697c41e2d7a61
DIFF: https://github.com/llvm/llvm-project/commit/2fb1324736f69391636297f973e697c41e2d7a61.diff

LOG: [RISCV] Add FMV_H_X/FMV_W_X/FCVT_H_W/FCVT_H_WU to isAllUsesReadW in SExtWRemoval.

The instructions only read the lower 16 or 32 bits of a GPR.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index bdc51326b7c8..14115982313a 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -118,6 +118,10 @@ static bool isAllUsesReadW(const MachineInstr &OrigMI,
     case RISCV::CTZW:
     case RISCV::CPOPW:
     case RISCV::SLLI_UW:
+    case RISCV::FMV_H_X:
+    case RISCV::FMV_W_X:
+    case RISCV::FCVT_H_W:
+    case RISCV::FCVT_H_WU:
     case RISCV::FCVT_S_W:
     case RISCV::FCVT_S_WU:
     case RISCV::FCVT_D_W: