[llvm] 4a6ef00 - [RISCV] Change SEXT_B/SEXT_H/ZEXT_H_RV64 handling in isAllUsesReadW in SExtWRemoval.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-03T23:59:08-07:00
New Revision: 4a6ef0078cd0ce5c6622cb141bca5cfb9bee5f22

URL: https://github.com/llvm/llvm-project/commit/4a6ef0078cd0ce5c6622cb141bca5cfb9bee5f22
DIFF: https://github.com/llvm/llvm-project/commit/4a6ef0078cd0ce5c6622cb141bca5cfb9bee5f22.diff

LOG: [RISCV] Change SEXT_B/SEXT_H/ZEXT_H_RV64 handling in isAllUsesReadW in SExtWRemoval.

These instrucitons only use the lower 8 or 16 bits. We don't need
to look across them.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index a31f898e104d..bdc51326b7c8 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -122,6 +122,9 @@ static bool isAllUsesReadW(const MachineInstr &OrigMI,
     case RISCV::FCVT_S_WU:
     case RISCV::FCVT_D_W:
     case RISCV::FCVT_D_WU:
+    case RISCV::SEXT_B:
+    case RISCV::SEXT_H:
+    case RISCV::ZEXT_H_RV64:
       continue;
 
     // these overwrite higher input bits, otherwise the lower word of output
@@ -167,8 +170,6 @@ static bool isAllUsesReadW(const MachineInstr &OrigMI,
     case RISCV::CLMUL:
     case RISCV::ORC_B:
     case RISCV::ORN:
-    case RISCV::SEXT_B:
-    case RISCV::SEXT_H:
     case RISCV::SH1ADD:
     case RISCV::SH1ADD_UW:
     case RISCV::SH2ADD:
@@ -176,7 +177,6 @@ static bool isAllUsesReadW(const MachineInstr &OrigMI,
     case RISCV::SH3ADD:
     case RISCV::SH3ADD_UW:
     case RISCV::XNOR:
-    case RISCV::ZEXT_H_RV64:
       addUses(*MI, Worklist, MRI);
       continue;
     default: