[llvm] 0eb2f66 - [RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 3 09:18:55 PDT 2022
Author: Michael Maitland
Date: 2022-11-03T09:18:42-07:00
New Revision: 0eb2f663d27432111e3f0f68a0d586ade4c8036e
URL: https://github.com/llvm/llvm-project/commit/0eb2f663d27432111e3f0f68a0d586ade4c8036e
DIFF: https://github.com/llvm/llvm-project/commit/0eb2f663d27432111e3f0f68a0d586ade4c8036e.diff
LOG: [RISCV][CodeGen] Account for LMUL for Vector Integer Arithmetic Instructions
It is likley that subtargets act differently for a vector integer arithmetic instruction based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL. It also
introduces the concept of an "UpperBound LMUL" which allows us to describe how an instruction should behave
when the LMUL is unknown. All base instructions use the UpperBound resources because they are not tied to
a specific LMUL. This gives subtargetes the flexibility to describe their own upper bounds on each vector
instruction.
I have a series of patches for the rest of the vector instruction set ready to go, but I would like to first
get feedback on the first one of the series (this one).
Differential Revision: https://reviews.llvm.org/D136730
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 65e36e0aa3b8c..1b4813720d97b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -402,97 +402,124 @@ multiclass VIndexLoadStore<list<int> EEWList> {
multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>;
+ Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>;
+ Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>;
+ Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
+ ReadVMask]>;
}
multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>;
+ Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>;
+ Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUX_UpperBound, ReadVMask]>;
}
multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUX, ReadVMask]>;
+ Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
+ ReadVIALUX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>;
+ Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
+ ReadVMask]>;
}
multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>;
+ Sched<[WriteVIWALUV_UpperBound, ReadVIWALUV_UpperBound,
+ ReadVIWALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>;
+ Sched<[WriteVIWALUX_UpperBound, ReadVIWALUV_UpperBound,
+ ReadVIWALUX_UpperBound, ReadVMask]>;
}
multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>;
+ Sched<[WriteVIMulAddV_UpperBound, ReadVIMulAddV_UpperBound,
+ ReadVIMulAddV_UpperBound, ReadVMask]>;
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>;
+ Sched<[WriteVIMulAddX_UpperBound, ReadVIMulAddV_UpperBound,
+ ReadVIMulAddX_UpperBound, ReadVMask]>;
}
multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>;
+ Sched<[WriteVIWMulAddV_UpperBound, ReadVIWMulAddV_UpperBound,
+ ReadVIWMulAddV_UpperBound, ReadVMask]>;
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>;
+ Sched<[WriteVIWMulAddX_UpperBound, ReadVIWMulAddV_UpperBound,
+ ReadVIWMulAddX_UpperBound, ReadVMask]>;
}
multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>;
+ Sched<[WriteVIWMulAddX_UpperBound, ReadVIWMulAddV_UpperBound,
+ ReadVIWMulAddX_UpperBound, ReadVMask]>;
}
multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
+ Sched<[WriteVExtV_UpperBound, ReadVExtV_UpperBound,
+ ReadVMask]>;
}
multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
+ Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
+ Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUX_UpperBound, ReadVMask]>;
def IM : VALUmVI<funct6, opcodestr # ".vim">,
- Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
+ Sched<[WriteVICALUI_UpperBound, ReadVICALUV_UpperBound,
+ ReadVMask]>;
}
multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>;
+ Sched<[WriteVIMergeV_UpperBound, ReadVIMergeV_UpperBound,
+ ReadVIMergeV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>;
+ Sched<[WriteVIMergeX_UpperBound, ReadVIMergeV_UpperBound,
+ ReadVIMergeX_UpperBound, ReadVMask]>;
def IM : VALUmVI<funct6, opcodestr # ".vim">,
- Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>;
+ Sched<[WriteVIMergeI_UpperBound, ReadVIMergeV_UpperBound,
+ ReadVMask]>;
}
multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
+ Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
+ Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUX_UpperBound, ReadVMask]>;
}
multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
+ Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUV_UpperBound]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
+ Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound
+ , ReadVICALUX_UpperBound]>;
def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>,
- Sched<[WriteVICALUI, ReadVICALUV]>;
+ Sched<[WriteVICALUI_UpperBound, ReadVICALUV_UpperBound]>;
}
multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
+ Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUV_UpperBound]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
+ Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUX_UpperBound]>;
}
multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
@@ -675,64 +702,83 @@ multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVShiftV, ReadVShiftV, ReadVShiftV, ReadVMask]>;
+ Sched<[WriteVShiftV_UpperBound, ReadVShiftV_UpperBound,
+ ReadVShiftV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVShiftX, ReadVShiftV, ReadVShiftX, ReadVMask]>;
+ Sched<[WriteVShiftX_UpperBound, ReadVShiftV_UpperBound,
+ ReadVShiftX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVShiftI, ReadVShiftV, ReadVMask]>;
+ Sched<[WriteVShiftI_UpperBound, ReadVShiftV_UpperBound,
+ ReadVMask]>;
}
multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVNShiftV, ReadVNShiftV, ReadVNShiftV, ReadVMask]>;
+ Sched<[WriteVNShiftV_UpperBound, ReadVNShiftV_UpperBound,
+ ReadVNShiftV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVNShiftX, ReadVNShiftV, ReadVNShiftX, ReadVMask]>;
+ Sched<[WriteVNShiftX_UpperBound, ReadVNShiftV_UpperBound,
+ ReadVNShiftX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVNShiftI, ReadVNShiftV, ReadVMask]>;
+ Sched<[WriteVNShiftI_UpperBound, ReadVNShiftV_UpperBound,
+ ReadVMask]>;
}
multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
+ Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
+ ReadVICmpV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
+ Sched<[WriteVICmpX_UpperBound, ReadVICmpV_UpperBound,
+ ReadVICmpX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
+ Sched<[WriteVICmpI_UpperBound, ReadVICmpV_UpperBound,
+ ReadVMask]>;
}
multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpX, ReadVMask]>;
+ Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
+ ReadVICmpX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
+ Sched<[WriteVICmpI_UpperBound, ReadVICmpV_UpperBound,
+ ReadVMask]>;
}
multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
+ Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
+ ReadVICmpV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
+ Sched<[WriteVICmpX_UpperBound, ReadVICmpV_UpperBound,
+ ReadVICmpX_UpperBound, ReadVMask]>;
}
multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIMulV, ReadVIMulV, ReadVIMulV, ReadVMask]>;
+ Sched<[WriteVIMulV_UpperBound, ReadVIMulV_UpperBound,
+ ReadVIMulV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIMulX, ReadVIMulV, ReadVIMulX, ReadVMask]>;
+ Sched<[WriteVIMulX_UpperBound, ReadVIMulV_UpperBound,
+ ReadVIMulX_UpperBound, ReadVMask]>;
}
multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIWMulV, ReadVIWMulV, ReadVIWMulV, ReadVMask]>;
+ Sched<[WriteVIWMulV_UpperBound, ReadVIWMulV_UpperBound,
+ ReadVIWMulV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIWMulX, ReadVIWMulV, ReadVIWMulX, ReadVMask]>;
+ Sched<[WriteVIWMulX_UpperBound, ReadVIWMulV_UpperBound,
+ ReadVIWMulX_UpperBound, ReadVMask]>;
}
multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVIDivV, ReadVIDivV, ReadVIDivV, ReadVMask]>;
+ Sched<[WriteVIDivV_UpperBound, ReadVIDivV_UpperBound,
+ ReadVIDivV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVIDivX, ReadVIDivV, ReadVIDivX, ReadVMask]>;
+ Sched<[WriteVIDivX_UpperBound, ReadVIDivV_UpperBound,
+ ReadVIDivX_UpperBound, ReadVMask]>;
}
multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
@@ -1126,15 +1172,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1,
// op vd, vs1
def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
(ins VR:$vs1), "vmv.v.v", "$vd, $vs1">,
- Sched<[WriteVIMovV, ReadVIMovV]>;
+ Sched<[WriteVIMovV_UpperBound, ReadVIMovV_UpperBound]>;
// op vd, rs1
def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
(ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
- Sched<[WriteVIMovX, ReadVIMovX]>;
+ Sched<[WriteVIMovX_UpperBound, ReadVIMovX_UpperBound]>;
// op vd, imm
def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
(ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
- Sched<[WriteVIMovI]>;
+ Sched<[WriteVIMovI_UpperBound]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Vector Fixed-Point Arithmetic Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 7c765dd3548bc..06169022a0fa5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1914,6 +1914,10 @@ multiclass VPseudoBinaryV_VV<string Constraint = ""> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
}
+multiclass VPseudoBinaryV_VV_LMUL<LMULInfo m, string Constraint = ""> {
+ defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
+}
+
// Similar to VPseudoBinaryV_VV, but uses MxListF.
multiclass VPseudoBinaryFV_VV<string Constraint = ""> {
foreach m = MxListF in
@@ -1941,6 +1945,10 @@ multiclass VPseudoBinaryV_VX<string Constraint = ""> {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
+multiclass VPseudoBinaryV_VX_LMUL<LMULInfo m, string Constraint = ""> {
+ defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
+}
+
multiclass VPseudoVSLD1_VX<string Constraint = ""> {
foreach m = MxList in
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
@@ -1967,6 +1975,10 @@ multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
}
+multiclass VPseudoBinaryV_VI_LMUL<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
+ defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+}
+
multiclass VPseudoVALU_MM {
foreach m = MxList in
let VLMul = m.value in {
@@ -1988,10 +2000,14 @@ multiclass VPseudoBinaryW_VV<list<LMULInfo> mxlist = MxListW> {
"@earlyclobber $rd">;
}
-multiclass VPseudoBinaryW_VX {
- foreach m = MxListW in
- defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
- "@earlyclobber $rd">;
+multiclass VPseudoBinaryW_VV_LMUL<LMULInfo m> {
+ defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
+ "@earlyclobber $rd">;
+}
+
+multiclass VPseudoBinaryW_VX_LMUL<LMULInfo m> {
+ defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
+ "@earlyclobber $rd">;
}
multiclass VPseudoBinaryW_VF {
@@ -2011,9 +2027,15 @@ multiclass VPseudoBinaryW_WV<list<LMULInfo> mxlist = MxListW> {
}
}
-multiclass VPseudoBinaryW_WX {
- foreach m = MxListW in
- defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
+multiclass VPseudoBinaryW_WV_LMUL<LMULInfo m> {
+ defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
+ "@earlyclobber $rd">;
+ defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
+ "@earlyclobber $rd">;
+}
+
+multiclass VPseudoBinaryW_WX_LMUL<LMULInfo m> {
+ defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
}
multiclass VPseudoBinaryW_WF {
@@ -2034,59 +2056,70 @@ multiclass VPseudoBinaryV_WV {
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
+multiclass VPseudoBinaryV_WV_LMUL<LMULInfo m> {
+ defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
multiclass VPseudoBinaryV_WX {
foreach m = MxListW in
defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
+multiclass VPseudoBinaryV_WX_LMUL<LMULInfo m> {
+ defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
multiclass VPseudoBinaryV_WI {
foreach m = MxListW in
defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
+multiclass VPseudoBinaryV_WI_LMUL<LMULInfo m> {
+ defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
// For vadc and vsbc, the instruction encoding is reserved if the destination
// vector register is v0.
// For vadc and vsbc, CarryIn == 1 and CarryOut == 0
-multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
- VPseudoBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, m.vrclass, m, CarryIn, Constraint>;
+ def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
+ VPseudoBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, m.vrclass, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" :
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, m.vrclass, m, CarryIn, Constraint>;
+ def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" :
+ VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, m.vrclass, m, CarryIn, Constraint>;
}
-multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
- VPseudoBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, GPR, m, CarryIn, Constraint>;
+ def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
+ VPseudoBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, GPR, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoTiedBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, GPR, m, CarryIn, Constraint>;
+ def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, GPR, m, CarryIn, Constraint>;
}
multiclass VPseudoVMRG_FM {
@@ -2104,41 +2137,48 @@ multiclass VPseudoVMRG_FM {
}
}
-multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
- VPseudoBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, simm5, m, CarryIn, Constraint>;
+ def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
+ VPseudoBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, simm5, m, CarryIn, Constraint>;
}
-multiclass VPseudoTiedBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
+multiclass VPseudoTiedBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
- foreach m = MxList in
- def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
- VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
- !if(!and(CarryIn, !not(CarryOut)),
- GetVRegNoV0<m.vrclass>.R, m.vrclass)),
- m.vrclass, simm5, m, CarryIn, Constraint>;
+ def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU":
+ VPseudoTiedBinaryCarryIn<!if(CarryOut, VR,
+ !if(!and(CarryIn, !not(CarryOut)),
+ GetVRegNoV0<m.vrclass>.R, m.vrclass)),
+ m.vrclass, simm5, m, CarryIn, Constraint>;
}
multiclass VPseudoUnaryVMV_V_X_I {
foreach m = MxList in {
let VLMul = m.value in {
- def "_V_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>,
- Sched<[WriteVIMovV, ReadVIMovV]>;
- def "_X_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, GPR>,
- Sched<[WriteVIMovX, ReadVIMovX]>;
- def "_I_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, simm5>,
- Sched<[WriteVIMovI]>;
- def "_V_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, m.vrclass>,
- Sched<[WriteVIMovV, ReadVIMovV]>;
- def "_X_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, GPR>,
- Sched<[WriteVIMovX, ReadVIMovX]>;
- def "_I_" # m.MX # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, simm5>,
- Sched<[WriteVIMovI]>;
+ defvar mx = m.MX;
+ defvar WriteVIMovV_MX = !cast<SchedWrite>("WriteVIMovV_" # mx);
+ defvar WriteVIMovX_MX = !cast<SchedWrite>("WriteVIMovX_" # mx);
+ defvar WriteVIMovI_MX = !cast<SchedWrite>("WriteVIMovI_" # mx);
+ defvar ReadVIMovV_MX = !cast<SchedRead>("ReadVIMovV_" # mx);
+ defvar ReadVIMovX_MX = !cast<SchedRead>("ReadVIMovX_" # mx);
+
+ let VLMul = m.value in {
+ def "_V_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>,
+ Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
+ def "_X_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, GPR>,
+ Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
+ def "_I_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, simm5>,
+ Sched<[WriteVIMovI_MX]>;
+ def "_V_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, m.vrclass>,
+ Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
+ def "_X_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, GPR>,
+ Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
+ def "_I_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, simm5>,
+ Sched<[WriteVIMovI_MX]>;
+ }
}
}
}
@@ -2204,15 +2244,19 @@ multiclass PseudoVEXT_VF2 {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF2 in
{
+ defvar mx = m.MX;
+ defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
+ defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+
let VLMul = m.value in {
- def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f2vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_MASK" :
+ def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f2vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
}
@@ -2221,15 +2265,19 @@ multiclass PseudoVEXT_VF4 {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF4 in
{
+ defvar mx = m.MX;
+ defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
+ defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+
let VLMul = m.value in {
- def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f4vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_MASK" :
+ def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f4vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
}
@@ -2238,15 +2286,19 @@ multiclass PseudoVEXT_VF8 {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF8 in
{
+ defvar mx = m.MX;
+ defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
+ defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
+
let VLMul = m.value in {
- def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f8vrclass, constraints>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
- def "_" # m.MX # "_MASK" :
+ def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f8vrclass, constraints>,
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
+ def "_" # mx # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
+ Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
}
@@ -2268,11 +2320,15 @@ multiclass VPseudoBinaryM_VV<list<LMULInfo> mxlist = MxList> {
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
}
-multiclass VPseudoBinaryM_VX {
- foreach m = MxList in
- defm "_VX" :
- VPseudoBinaryM<VR, m.vrclass, GPR, m,
- !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
+multiclass VPseudoBinaryM_VV_LMUL<LMULInfo m> {
+ defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
+ !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
+}
+
+multiclass VPseudoBinaryM_VX<LMULInfo m> {
+ defm "_VX" :
+ VPseudoBinaryM<VR, m.vrclass, GPR, m,
+ !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
}
multiclass VPseudoBinaryM_VF {
@@ -2283,10 +2339,9 @@ multiclass VPseudoBinaryM_VF {
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
}
-multiclass VPseudoBinaryM_VI {
- foreach m = MxList in
- defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
- !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
+multiclass VPseudoBinaryM_VI<LMULInfo m> {
+ defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
+ !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
}
multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
@@ -2309,12 +2364,21 @@ multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
- defm "" : VPseudoBinaryV_VV<Constraint>,
- Sched<[WriteVShiftV, ReadVShiftV, ReadVShiftV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX<Constraint>,
- Sched<[WriteVShiftX, ReadVShiftV, ReadVShiftX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
- Sched<[WriteVShiftI, ReadVShiftV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVShiftV_MX = !cast<SchedWrite>("WriteVShiftV_" # mx);
+ defvar WriteVShiftX_MX = !cast<SchedWrite>("WriteVShiftX_" # mx);
+ defvar WriteVShiftI_MX = !cast<SchedWrite>("WriteVShiftI_" # mx);
+ defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
+ defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
@@ -2327,12 +2391,21 @@ multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
}
multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
- defm "" : VPseudoBinaryV_VV<Constraint>,
- Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX<Constraint>,
- Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
- Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
+ defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUX_" # mx);
+ defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
+ defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
+ defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVSALU_VV_VX {
@@ -2357,24 +2430,48 @@ multiclass VPseudoVAALU_VV_VX {
}
multiclass VPseudoVMINMAX_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
+ defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
+ defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
+ defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVMUL_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVIMulV, ReadVIMulV, ReadVIMulV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVIMulX, ReadVIMulV, ReadVIMulX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIMulV_MX = !cast<SchedWrite>("WriteVIMulV_" # mx);
+ defvar WriteVIMulX_MX = !cast<SchedWrite>("WriteVIMulX_" # mx);
+ defvar ReadVIMulV_MX = !cast<SchedRead>("ReadVIMulV_" # mx);
+ defvar ReadVIMulX_MX = !cast<SchedRead>("ReadVIMulX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVIMulV_MX, ReadVIMulV_MX, ReadVIMulV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVDIV_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVIDivV, ReadVIDivV, ReadVIDivV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVIDivX, ReadVIDivV, ReadVIDivX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIDivV_MX = !cast<SchedWrite>("WriteVIDivV_" # mx);
+ defvar WriteVIDivX_MX = !cast<SchedWrite>("WriteVIDivX_" # mx);
+ defvar ReadVIDivV_MX = !cast<SchedRead>("ReadVIDivV_" # mx);
+ defvar ReadVIDivX_MX = !cast<SchedRead>("ReadVIDivX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVIDivV_MX, ReadVIDivV_MX, ReadVIDivV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVIDivX_MX, ReadVIDivV_MX, ReadVIDivX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVFMUL_VV_VF {
@@ -2397,10 +2494,18 @@ multiclass VPseudoVFRDIV_VF {
}
multiclass VPseudoVALU_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
+ defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
+ defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
+ defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVSGNJ_VV_VF {
@@ -2430,24 +2535,48 @@ multiclass VPseudoVALU_VF {
}
multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI<ImmType>,
- Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUX_" # mx);
+ defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
+ defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
+ defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m>,
+ Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVWALU_VV_VX {
- defm "" : VPseudoBinaryW_VV,
- Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>;
- defm "" : VPseudoBinaryW_VX,
- Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVIWALUV_MX = !cast<SchedWrite>("WriteVIWALUV_" # mx);
+ defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
+ defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
+ defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
+
+ defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryW_VX_LMUL<m>,
+ Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVWMUL_VV_VX {
- defm "" : VPseudoBinaryW_VV,
- Sched<[WriteVIWMulV, ReadVIWMulV, ReadVIWMulV, ReadVMask]>;
- defm "" : VPseudoBinaryW_VX,
- Sched<[WriteVIWMulX, ReadVIWMulV, ReadVIWMulX, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVIWMulV_MX = !cast<SchedWrite>("WriteVIWMulV_" # mx);
+ defvar WriteVIWMulX_MX = !cast<SchedWrite>("WriteVIWMulX_" # mx);
+ defvar ReadVIWMulV_MX = !cast<SchedRead>("ReadVIWMulV_" # mx);
+ defvar ReadVIWMulX_MX = !cast<SchedRead>("ReadVIWMulX_" # mx);
+
+ defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ Sched<[WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryW_VX_LMUL<m>,
+ Sched<[WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVWMUL_VV_VF {
@@ -2458,10 +2587,18 @@ multiclass VPseudoVWMUL_VV_VF {
}
multiclass VPseudoVWALU_WV_WX {
- defm "" : VPseudoBinaryW_WV,
- Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>;
- defm "" : VPseudoBinaryW_WX,
- Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVIWALUV_MX = !cast<SchedWrite>("WriteVIWALUV_" # mx);
+ defvar WriteVIWALUX_MX = !cast<SchedWrite>("WriteVIWALUX_" # mx);
+ defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
+ defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
+
+ defm "" : VPseudoBinaryW_WV_LMUL<m>,
+ Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryW_WX_LMUL<m>,
+ Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVFWALU_VV_VF {
@@ -2479,79 +2616,139 @@ multiclass VPseudoVFWALU_WV_WF {
}
multiclass VPseudoVMRG_VM_XM_IM {
- defm "" : VPseudoBinaryV_VM,
- Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM,
- Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>;
- defm "" : VPseudoBinaryV_IM,
- Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>;
- // Tied versions to allow codegen control over the tail elements
- defm "" : VPseudoTiedBinaryV_VM,
- Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_XM,
- Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_IM,
- Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIMergeV_MX = !cast<SchedWrite>("WriteVIMergeV_" # mx);
+ defvar WriteVIMergeX_MX = !cast<SchedWrite>("WriteVIMergeX_" # mx);
+ defvar WriteVIMergeI_MX = !cast<SchedWrite>("WriteVIMergeI_" # mx);
+ defvar ReadVIMergeV_MX = !cast<SchedRead>("ReadVIMergeV_" # mx);
+ defvar ReadVIMergeX_MX = !cast<SchedRead>("ReadVIMergeX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m>,
+ Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_XM<m>,
+ Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_IM<m>,
+ Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
+ // Tied versions to allow codegen control over the tail elements
+ defm "" : VPseudoTiedBinaryV_VM<m>,
+ Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
+ defm "" : VPseudoTiedBinaryV_XM<m>,
+ Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
+ defm "" : VPseudoTiedBinaryV_IM<m>,
+ Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCALU_VM_XM_IM {
- defm "" : VPseudoBinaryV_VM,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
- defm "" : VPseudoBinaryV_IM,
- Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
- // Tied versions to allow codegen control over the tail elements
- defm "" : VPseudoTiedBinaryV_VM,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_XM,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_IM,
- Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_XM<m>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_IM<m>,
+ Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
+ // Tied versions to allow codegen control over the tail elements
+ defm "" : VPseudoTiedBinaryV_VM<m>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoTiedBinaryV_XM<m>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ defm "" : VPseudoTiedBinaryV_IM<m>,
+ Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCALU_VM_XM {
- defm "" : VPseudoBinaryV_VM,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
- // Tied versions to allow codegen control over the tail elements
- defm "" : VPseudoTiedBinaryV_VM,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoTiedBinaryV_XM,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_XM<m>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ // Tied versions to allow codegen control over the tail elements
+ defm "" : VPseudoTiedBinaryV_VM<m>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoTiedBinaryV_XM<m>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
- defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
- defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUI, ReadVICALUV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_IM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCALUM_VM_XM<string Constraint> {
- defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCALUM_V_X_I<string Constraint> {
- defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
- defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
- defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUI, ReadVICALUV]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar WriteVICALUI_MX = !cast<SchedWrite>("WriteVICALUI_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
+ defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
+ defm "" : VPseudoBinaryV_IM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ Sched<[WriteVICALUI_MX, ReadVICALUV_MX]>;
+ }
}
multiclass VPseudoVCALUM_V_X<string Constraint> {
- defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUV, ReadVICALUV, ReadVICALUV]>;
- defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
- Sched<[WriteVICALUX, ReadVICALUV, ReadVICALUX]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
+ defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);
+ defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
+ defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
+ defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
+ }
}
multiclass VPseudoVNCLP_WV_WX_WI {
@@ -2564,12 +2761,21 @@ multiclass VPseudoVNCLP_WV_WX_WI {
}
multiclass VPseudoVNSHT_WV_WX_WI {
- defm "" : VPseudoBinaryV_WV,
- Sched<[WriteVNShiftV, ReadVNShiftV, ReadVNShiftV, ReadVMask]>;
- defm "" : VPseudoBinaryV_WX,
- Sched<[WriteVNShiftX, ReadVNShiftV, ReadVNShiftX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WI,
- Sched<[WriteVNShiftI, ReadVNShiftV, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVNShiftV_MX = !cast<SchedWrite>("WriteVNShiftV_" # mx);
+ defvar WriteVNShiftX_MX = !cast<SchedWrite>("WriteVNShiftX_" # mx);
+ defvar WriteVNShiftI_MX = !cast<SchedWrite>("WriteVNShiftI_" # mx);
+ defvar ReadVNShiftV_MX = !cast<SchedRead>("ReadVNShiftV_" # mx);
+ defvar ReadVNShiftX_MX = !cast<SchedRead>("ReadVNShiftX_" # mx);
+
+ defm "" : VPseudoBinaryV_WV_LMUL<m>,
+ Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_WX_LMUL<m>,
+ Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_WI_LMUL<m>,
+ Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoTernary<VReg RetClass,
@@ -2617,15 +2823,19 @@ multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "",
}
}
+multiclass VPseudoTernaryV_VV_AAXA_LMUL<LMULInfo m, string Constraint = ""> {
+ defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
+ Constraint, /*Commutable*/1>;
+}
+
multiclass VPseudoVSLDV_VX<string Constraint = ""> {
foreach m = MxList in
defm _VX : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
-multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
- foreach m = MxList in
- defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
- Constraint, /*Commutable*/1>;
+multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
+ defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
+ Constraint, /*Commutable*/1>;
}
multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> {
@@ -2643,11 +2853,16 @@ multiclass VPseudoTernaryW_VV<list<LMULInfo> mxlist = MxListW> {
constraint>;
}
-multiclass VPseudoTernaryW_VX {
+multiclass VPseudoTernaryW_VV_LMUL<LMULInfo m> {
defvar constraint = "@earlyclobber $rd";
- foreach m = MxListW in
- defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,
- constraint>;
+ defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
+ constraint>;
+}
+
+multiclass VPseudoTernaryW_VX<LMULInfo m> {
+ defvar constraint = "@earlyclobber $rd";
+ defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,
+ constraint>;
}
multiclass VPseudoTernaryW_VF {
@@ -2664,10 +2879,20 @@ multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, string Constraint = ""> {
}
multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
- defm "" : VPseudoTernaryV_VV_AAXA<Constraint>,
- Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>;
- defm "" : VPseudoTernaryV_VX_AAXA<Constraint>,
- Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVIMulAddV_MX = !cast<SchedWrite>("WriteVIMulAddV_" # mx);
+ defvar WriteVIMulAddX_MX = !cast<SchedWrite>("WriteVIMulAddX_" # mx);
+ defvar ReadVIMulAddV_MX = !cast<SchedRead>("ReadVIMulAddV_" # mx);
+ defvar ReadVIMulAddX_MX = !cast<SchedRead>("ReadVIMulAddX_" # mx);
+
+ defm "" : VPseudoTernaryV_VV_AAXA_LMUL<m, Constraint>,
+ Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
+ ReadVIMulAddV_MX, ReadVMask]>;
+ defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>,
+ Sched<[WriteVIMulAddX_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
+ ReadVIMulAddX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVMAC_VV_VF_AAXA<string Constraint = ""> {
@@ -2685,15 +2910,33 @@ multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
}
multiclass VPseudoVWMAC_VV_VX {
- defm "" : VPseudoTernaryW_VV,
- Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>;
- defm "" : VPseudoTernaryW_VX,
- Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVIWMulAddV_MX = !cast<SchedWrite>("WriteVIWMulAddV_" # mx);
+ defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
+ defvar ReadVIWMulAddV_MX = !cast<SchedRead>("ReadVIWMulAddV_" # mx);
+ defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
+
+ defm "" : VPseudoTernaryW_VV_LMUL<m>,
+ Sched<[WriteVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
+ ReadVIWMulAddV_MX, ReadVMask]>;
+ defm "" : VPseudoTernaryW_VX<m>,
+ Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
+ ReadVIWMulAddX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVWMAC_VX {
- defm "" : VPseudoTernaryW_VX,
- Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVIWMulAddX_MX = !cast<SchedWrite>("WriteVIWMulAddX_" # mx);
+ defvar ReadVIWMulAddV_MX= !cast<SchedRead>("ReadVIWMulAddV_" # mx);
+ defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
+
+ defm "" : VPseudoTernaryW_VX<m>,
+ Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
+ ReadVIWMulAddX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVWMAC_VV_VF {
@@ -2704,19 +2947,36 @@ multiclass VPseudoVWMAC_VV_VF {
}
multiclass VPseudoVCMPM_VV_VX_VI {
- defm "" : VPseudoBinaryM_VV,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
- defm "" : VPseudoBinaryM_VX,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
- defm "" : VPseudoBinaryM_VI,
- Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
+ defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
+ defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
+ defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
+ defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+
+ defm "" : VPseudoBinaryM_VV_LMUL<m>,
+ Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryM_VX<m>,
+ Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryM_VI<m>,
+ Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCMPM_VV_VX {
- defm "" : VPseudoBinaryM_VV,
- Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
- defm "" : VPseudoBinaryM_VX,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
+ defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
+ defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
+ defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+
+ defm "" : VPseudoBinaryM_VV_LMUL<m>,
+ Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryM_VX<m>,
+ Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVCMPM_VV_VF {
@@ -2732,10 +2992,18 @@ multiclass VPseudoVCMPM_VF {
}
multiclass VPseudoVCMPM_VX_VI {
- defm "" : VPseudoBinaryM_VX,
- Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>;
- defm "" : VPseudoBinaryM_VI,
- Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
+ defvar WriteVICmpI_MX = !cast<SchedWrite>("WriteVICmpI_" # mx);
+ defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
+ defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
+
+ defm "" : VPseudoBinaryM_VX<m>,
+ Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryM_VI<m>,
+ Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVRED_VS {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 3c5b48803f4c4..013b9bd61455a 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,6 +9,41 @@
//===----------------------------------------------------------------------===//
/// Define scheduler resources associated with def operands.
+defvar SchedMxList = ["UpperBound", "M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
+// Used for widening and narrowing instructions as it doesn't contain M8.
+defvar SchedMxListW = ["UpperBound", "MF8", "MF4", "MF2", "M1", "M2", "M4"];
+
+// Creates SchedWrite for each (name, LMUL) pair for LMUL in lmuls argument
+multiclass LMULSchedWrites<string name, list<string> lmuls = SchedMxList> {
+ foreach mx = lmuls in {
+ def name # "_" # mx : SchedWrite;
+ }
+}
+
+// Creates SchedRead for each (name, LMUL) pair for LMUL in lmuls argument
+multiclass LMULSchedReads<string name, list<string> lmuls = SchedMxList> {
+ foreach mx = lmuls in {
+ def name # "_" # mx : SchedRead;
+ }
+}
+
+// Creates WriteRes for each (name, LMUL, resources) tuple for LMUL
+// in lmuls argument
+multiclass LMULWriteRes<string name, list<ProcResourceKind> resources,
+ list<string> lmuls = SchedMxList> {
+ foreach mx = lmuls in {
+ def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+ }
+}
+
+// Creates ReadAdvance for each (name, LMUL, val) tuple for LMUL
+// in lmuls argument
+multiclass LMULReadAdvance<string name, int val, list<string> lmuls = SchedMxList> {
+ foreach mx = lmuls in {
+ def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val>;
+ }
+}
+
// 3.6 Vector Byte Length vlenb
def WriteRdVLENB : SchedWrite;
@@ -79,55 +114,55 @@ def WriteVST8R : SchedWrite;
// 11. Vector Integer Arithmetic Instructions
// 11.1. Vector Single-Width Integer Add and Subtract
// 11.5. Vector Bitwise Logical Instructions
-def WriteVIALUV : SchedWrite;
-def WriteVIALUX : SchedWrite;
-def WriteVIALUI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIALUV">;
+defm "" : LMULSchedWrites<"WriteVIALUX">;
+defm "" : LMULSchedWrites<"WriteVIALUI">;
// 11.2. Vector Widening Integer Add/Subtract
-def WriteVIWALUV : SchedWrite;
-def WriteVIWALUX : SchedWrite;
-def WriteVIWALUI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIWALUV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVIWALUX", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVIWALUI", SchedMxListW>;
// 11.3. Vector Integer Extension
-def WriteVExtV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVExtV">;
// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
-def WriteVICALUV : SchedWrite;
-def WriteVICALUX : SchedWrite;
-def WriteVICALUI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVICALUV">;
+defm "" : LMULSchedWrites<"WriteVICALUX">;
+defm "" : LMULSchedWrites<"WriteVICALUI">;
// 11.6. Vector Single-Width Bit Shift Instructions
-def WriteVShiftV : SchedWrite;
-def WriteVShiftX : SchedWrite;
-def WriteVShiftI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVShiftV">;
+defm "" : LMULSchedWrites<"WriteVShiftX">;
+defm "" : LMULSchedWrites<"WriteVShiftI">;
// 11.7. Vector Narrowing Integer Right Shift Instructions
-def WriteVNShiftV : SchedWrite;
-def WriteVNShiftX : SchedWrite;
-def WriteVNShiftI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVNShiftV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNShiftX", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNShiftI", SchedMxListW>;
// 11.8. Vector Integer Comparison Instructions
// 11.9. Vector Integer Min/Max Instructions
-def WriteVICmpV : SchedWrite;
-def WriteVICmpX : SchedWrite;
-def WriteVICmpI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVICmpV">;
+defm "" : LMULSchedWrites<"WriteVICmpX">;
+defm "" : LMULSchedWrites<"WriteVICmpI">;
// 11.10. Vector Single-Width Integer Multiply Instructions
-def WriteVIMulV : SchedWrite;
-def WriteVIMulX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIMulV">;
+defm "" : LMULSchedWrites<"WriteVIMulX">;
// 11.11. Vector Integer Divide Instructions
-def WriteVIDivV : SchedWrite;
-def WriteVIDivX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIDivV">;
+defm "" : LMULSchedWrites<"WriteVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions
-def WriteVIWMulV : SchedWrite;
-def WriteVIWMulX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIWMulV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVIWMulX", SchedMxListW>;
// 11.13. Vector Single-Width Integer Multiply-Add Instructions
-def WriteVIMulAddV : SchedWrite;
-def WriteVIMulAddX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIMulAddV">;
+defm "" : LMULSchedWrites<"WriteVIMulAddX">;
// 11.14. Vector Widening Integer Multiply-Add Instructions
-def WriteVIWMulAddV : SchedWrite;
-def WriteVIWMulAddX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIWMulAddV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVIWMulAddX", SchedMxListW>;
// 11.15. Vector Integer Merge Instructions
-def WriteVIMergeV : SchedWrite;
-def WriteVIMergeX : SchedWrite;
-def WriteVIMergeI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIMergeV">;
+defm "" : LMULSchedWrites<"WriteVIMergeX">;
+defm "" : LMULSchedWrites<"WriteVIMergeI">;
// 11.16. Vector Integer Move Instructions
-def WriteVIMovV : SchedWrite;
-def WriteVIMovX : SchedWrite;
-def WriteVIMovI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVIMovV">;
+defm "" : LMULSchedWrites<"WriteVIMovX">;
+defm "" : LMULSchedWrites<"WriteVIMovI">;
// 12. Vector Fixed-Point Arithmetic Instructions
// 12.1. Vector Single-Width Saturating Add and Subtract
@@ -303,47 +338,47 @@ def ReadVST8R : SchedRead;
// 11. Vector Integer Arithmetic Instructions
// 11.1. Vector Single-Width Integer Add and Subtract
// 11.5. Vector Bitwise Logical Instructions
-def ReadVIALUV : SchedRead;
-def ReadVIALUX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIALUV">;
+defm "" : LMULSchedReads<"ReadVIALUX">;
// 11.2. Vector Widening Integer Add/Subtract
-def ReadVIWALUV : SchedRead;
-def ReadVIWALUX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIWALUV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVIWALUX", SchedMxListW>;
// 11.3. Vector Integer Extension
-def ReadVExtV : SchedRead;
+defm "" : LMULSchedReads<"ReadVExtV">;
// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
-def ReadVICALUV : SchedRead;
-def ReadVICALUX : SchedRead;
+defm "" : LMULSchedReads<"ReadVICALUV">;
+defm "" : LMULSchedReads<"ReadVICALUX">;
// 11.6. Vector Single-Width Bit Shift Instructions
-def ReadVShiftV : SchedRead;
-def ReadVShiftX : SchedRead;
+defm "" : LMULSchedReads<"ReadVShiftV">;
+defm "" : LMULSchedReads<"ReadVShiftX">;
// 11.7. Vector Narrowing Integer Right Shift Instructions
-def ReadVNShiftV : SchedRead;
-def ReadVNShiftX : SchedRead;
+defm "" : LMULSchedReads<"ReadVNShiftV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVNShiftX", SchedMxListW>;
// 11.8. Vector Integer Comparison Instructions
// 11.9. Vector Integer Min/Max Instructions
-def ReadVICmpV : SchedRead;
-def ReadVICmpX : SchedRead;
+defm "" : LMULSchedReads<"ReadVICmpV">;
+defm "" : LMULSchedReads<"ReadVICmpX">;
// 11.10. Vector Single-Width Integer Multiply Instructions
-def ReadVIMulV : SchedRead;
-def ReadVIMulX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIMulV">;
+defm "" : LMULSchedReads<"ReadVIMulX">;
// 11.11. Vector Integer Divide Instructions
-def ReadVIDivV : SchedRead;
-def ReadVIDivX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIDivV">;
+defm "" : LMULSchedReads<"ReadVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions
-def ReadVIWMulV : SchedRead;
-def ReadVIWMulX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIWMulV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVIWMulX", SchedMxListW>;
// 11.13. Vector Single-Width Integer Multiply-Add Instructions
-def ReadVIMulAddV : SchedRead;
-def ReadVIMulAddX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIMulAddV">;
+defm "" : LMULSchedReads<"ReadVIMulAddX">;
// 11.14. Vector Widening Integer Multiply-Add Instructions
-def ReadVIWMulAddV : SchedRead;
-def ReadVIWMulAddX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIWMulAddV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVIWMulAddX", SchedMxListW>;
// 11.15. Vector Integer Merge Instructions
-def ReadVIMergeV : SchedRead;
-def ReadVIMergeX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIMergeV">;
+defm "" : LMULSchedReads<"ReadVIMergeX">;
// 11.16. Vector Integer Move Instructions
-def ReadVIMovV : SchedRead;
-def ReadVIMovX : SchedRead;
+defm "" : LMULSchedReads<"ReadVIMovV">;
+defm "" : LMULSchedReads<"ReadVIMovX">;
// 12. Vector Fixed-Point Arithmetic Instructions
// 12.1. Vector Single-Width Saturating Add and Subtract
@@ -541,42 +576,42 @@ foreach nf=2-8 in {
}
}
-// 12. Vector Integer Arithmetic Instructions
-def : WriteRes<WriteVIALUV, []>;
-def : WriteRes<WriteVIALUX, []>;
-def : WriteRes<WriteVIALUI, []>;
-def : WriteRes<WriteVIWALUV, []>;
-def : WriteRes<WriteVIWALUX, []>;
-def : WriteRes<WriteVIWALUI, []>;
-def : WriteRes<WriteVExtV, []>;
-def : WriteRes<WriteVICALUV, []>;
-def : WriteRes<WriteVICALUX, []>;
-def : WriteRes<WriteVICALUI, []>;
-def : WriteRes<WriteVShiftV, []>;
-def : WriteRes<WriteVShiftX, []>;
-def : WriteRes<WriteVShiftI, []>;
-def : WriteRes<WriteVNShiftV, []>;
-def : WriteRes<WriteVNShiftX, []>;
-def : WriteRes<WriteVNShiftI, []>;
-def : WriteRes<WriteVICmpV, []>;
-def : WriteRes<WriteVICmpX, []>;
-def : WriteRes<WriteVICmpI, []>;
-def : WriteRes<WriteVIMulV, []>;
-def : WriteRes<WriteVIMulX, []>;
-def : WriteRes<WriteVIDivV, []>;
-def : WriteRes<WriteVIDivX, []>;
-def : WriteRes<WriteVIWMulV, []>;
-def : WriteRes<WriteVIWMulX, []>;
-def : WriteRes<WriteVIMulAddV, []>;
-def : WriteRes<WriteVIMulAddX, []>;
-def : WriteRes<WriteVIWMulAddV, []>;
-def : WriteRes<WriteVIWMulAddX, []>;
-def : WriteRes<WriteVIMergeV, []>;
-def : WriteRes<WriteVIMergeX, []>;
-def : WriteRes<WriteVIMergeI, []>;
-def : WriteRes<WriteVIMovV, []>;
-def : WriteRes<WriteVIMovX, []>;
-def : WriteRes<WriteVIMovI, []>;
+// 11. Vector Integer Arithmetic Instructions
+defm "" : LMULWriteRes<"WriteVIALUV", []>;
+defm "" : LMULWriteRes<"WriteVIALUX", []>;
+defm "" : LMULWriteRes<"WriteVIALUI", []>;
+defm "" : LMULWriteRes<"WriteVIWALUV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIWALUX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIWALUI", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVExtV", []>;
+defm "" : LMULWriteRes<"WriteVICALUV", []>;
+defm "" : LMULWriteRes<"WriteVICALUX", []>;
+defm "" : LMULWriteRes<"WriteVICALUI", []>;
+defm "" : LMULWriteRes<"WriteVShiftV", []>;
+defm "" : LMULWriteRes<"WriteVShiftX", []>;
+defm "" : LMULWriteRes<"WriteVShiftI", []>;
+defm "" : LMULWriteRes<"WriteVNShiftV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNShiftX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNShiftI", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVICmpV", []>;
+defm "" : LMULWriteRes<"WriteVICmpX", []>;
+defm "" : LMULWriteRes<"WriteVICmpI", []>;
+defm "" : LMULWriteRes<"WriteVIMulV", []>;
+defm "" : LMULWriteRes<"WriteVIMulX", []>;
+defm "" : LMULWriteRes<"WriteVIDivV", []>;
+defm "" : LMULWriteRes<"WriteVIDivX", []>;
+defm "" : LMULWriteRes<"WriteVIWMulV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIWMulX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
+defm "" : LMULWriteRes<"WriteVIMulAddX", []>;
+defm "" : LMULWriteRes<"WriteVIWMulAddV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIWMulAddX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVIMergeV", []>;
+defm "" : LMULWriteRes<"WriteVIMergeX", []>;
+defm "" : LMULWriteRes<"WriteVIMergeI", []>;
+defm "" : LMULWriteRes<"WriteVIMovV", []>;
+defm "" : LMULWriteRes<"WriteVIMovX", []>;
+defm "" : LMULWriteRes<"WriteVIMovI", []>;
// 13. Vector Fixed-Point Arithmetic Instructions
def : WriteRes<WriteVSALUV, []>;
@@ -700,34 +735,34 @@ def : ReadAdvance<ReadVST2R, 0>;
def : ReadAdvance<ReadVST4R, 0>;
def : ReadAdvance<ReadVST8R, 0>;
-// 12. Vector Integer Arithmetic Instructions
-def : ReadAdvance<ReadVIALUV, 0>;
-def : ReadAdvance<ReadVIALUX, 0>;
-def : ReadAdvance<ReadVIWALUV, 0>;
-def : ReadAdvance<ReadVIWALUX, 0>;
-def : ReadAdvance<ReadVExtV, 0>;
-def : ReadAdvance<ReadVICALUV, 0>;
-def : ReadAdvance<ReadVICALUX, 0>;
-def : ReadAdvance<ReadVShiftV, 0>;
-def : ReadAdvance<ReadVShiftX, 0>;
-def : ReadAdvance<ReadVNShiftV, 0>;
-def : ReadAdvance<ReadVNShiftX, 0>;
-def : ReadAdvance<ReadVICmpV, 0>;
-def : ReadAdvance<ReadVICmpX, 0>;
-def : ReadAdvance<ReadVIMulV, 0>;
-def : ReadAdvance<ReadVIMulX, 0>;
-def : ReadAdvance<ReadVIDivV, 0>;
-def : ReadAdvance<ReadVIDivX, 0>;
-def : ReadAdvance<ReadVIWMulV, 0>;
-def : ReadAdvance<ReadVIWMulX, 0>;
-def : ReadAdvance<ReadVIMulAddV, 0>;
-def : ReadAdvance<ReadVIMulAddX, 0>;
-def : ReadAdvance<ReadVIWMulAddV, 0>;
-def : ReadAdvance<ReadVIWMulAddX, 0>;
-def : ReadAdvance<ReadVIMergeV, 0>;
-def : ReadAdvance<ReadVIMergeX, 0>;
-def : ReadAdvance<ReadVIMovV, 0>;
-def : ReadAdvance<ReadVIMovX, 0>;
+// 11. Vector Integer Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVIALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVIALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVIWALUV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVIWALUX", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVExtV", 0>;
+defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
+defm "" : LMULReadAdvance<"ReadVNShiftV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVNShiftX", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVIDivV", 0>;
+defm "" : LMULReadAdvance<"ReadVIDivX", 0>;
+defm "" : LMULReadAdvance<"ReadVIWMulV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVIWMulX", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm "" : LMULReadAdvance<"ReadVIWMulAddV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVIWMulAddX", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
+defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
// 13. Vector Fixed-Point Arithmetic Instructions
def : ReadAdvance<ReadVSALUV, 0>;
More information about the llvm-commits
mailing list