[PATCH] D135102: [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I read through the code. I'm not the biggest expert on this DAGToDAG code, but what is here seems sensible to me. All the tests look OK too.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2872
+  EVT VT = N->getValueType(0);
+  assert(VT == MVT::i32 || VT == MVT::i64);
+  SDLoc DL(N);
----------------
LLVM usually adds message to all assert messages. It can help distinguish them especially when the condition is fairly generic.


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Comment at: llvm/test/CodeGen/AArch64/trunc-to-tbl.ll:238
 
 define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) {
+; CHECK-LABEL: trunc_v16i64_to_v16i8_in_loop:
----------------
mingmingl wrote:
> This test case is generated by `utils/update_llc_test_checks.py`; but for some reason, the whitespaces cause more diff than expected.
> 
> I'm going to run auto updater in a clean branch, and see if the whitespace diff is expected without this patch.
Feel free to regenerate the files that need it and check those in to reduce the differences here.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135102/new/

https://reviews.llvm.org/D135102