[PATCH] D136918: [AMDGPU] Scheduler: fix RP calculation for a MBB with one successor

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

In D136918#3898811 <https://reviews.llvm.org/D136918#3898811>, @foad wrote:

>> at the beginning of bb.2.Flow %47 has 0x3F lane mask due to 928B %47:vreg_96 = IMAGE_SAMPLE_V3_V2 ...
>
> For this example. how much of %47 is really live at the beginning of bb.2.Flow? I.e. are there uses of all lanes of %47 in that bb or its successors?

Full %47 is used in bb.5.endif which is the successor of bb.2.Flow:

  1088B bb.5.endif:	; predecessors: %bb.2, %bb.3
  1136B	  ...
  1168B	  EXP_DONE 0, %47.sub0:vreg_96, %47.sub1:vreg_96, %47.sub2:vreg_96, %49:vgpr_32, -1, 0, 15, implicit $exec



> (Liveness is really "due to" uses, not defs.)

This sounds like if we need to track RP upward from uses to defs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136918/new/

https://reviews.llvm.org/D136918