[PATCH] D136918: [AMDGPU] Scheduler: fix RP calculation for a MBB with one successor

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> at the beginning of bb.2.Flow %47 has 0x3F lane mask due to 928B %47:vreg_96 = IMAGE_SAMPLE_V3_V2 ...

For this example. how much of %47 is really live at the beginning of bb.2.Flow? I.e. are there uses of all lanes of %47 in that bb or its successors? (Liveness is really "due to" uses, not defs.)


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  https://reviews.llvm.org/D136918/new/

https://reviews.llvm.org/D136918