[PATCH] D136447: [ARM] Fix vector ule zero lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> Normalizing wouldn't be entirely unprecedented in my understanding, after all we have e.g. a number of files `llvm/lib/CodeGen/SelectionDAG/Legalize*`. But this here also works for me.

We shouldn't leave parts of the code broken if we can fix them. Even if it was made reliable now, we don't know how the canonicalisation can change in the future.



================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:15209-15218
   // vcmp X, 0, cc -> vcmpz X, cc
   if (isZeroVector(Op1))
     return DAG.getNode(ARMISD::VCMPZ, dl, VT, Op0, N->getOperand(2));
 
   unsigned SwappedCond = getSwappedCondition(Cond);
   if (isValidMVECond(SwappedCond, VT.isFloatingPoint())) {
     // vcmp 0, X, cc -> vcmpz X, reversed(cc)
----------------
aaronpuchert wrote:
> Does something need to be done here?
Hmm. Don't think so. What kind of thing do you mean?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136447/new/

https://reviews.llvm.org/D136447