[PATCH] D136447: [ARM] Fix vector ule zero lowering

[Aaron Puchert via Phabricator via llvm-commits]

aaronpuchert added a comment.

In D136447#3874695 <https://reviews.llvm.org/D136447#3874695>, @dmgreen wrote:

> Do you mean converting ule 0 -> eq 0? I wanted the code here to be correct without needing it.

Normalizing wouldn't be entirely unprecedented in my understanding, after all we have e.g. a number of files `llvm/lib/CodeGen/SelectionDAG/Legalize*`. But this here also works for me.



================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:15209-15218
   // vcmp X, 0, cc -> vcmpz X, cc
   if (isZeroVector(Op1))
     return DAG.getNode(ARMISD::VCMPZ, dl, VT, Op0, N->getOperand(2));
 
   unsigned SwappedCond = getSwappedCondition(Cond);
   if (isValidMVECond(SwappedCond, VT.isFloatingPoint())) {
     // vcmp 0, X, cc -> vcmpz X, reversed(cc)
----------------
Does something need to be done here?


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  https://reviews.llvm.org/D136447/new/

https://reviews.llvm.org/D136447