[PATCH] D124195: [AMDGPU] Separate out SGPR spills to VGPR lanes during PEI

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1295-1301
+  // Mark all lane VGPRs as BB LiveIns.
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getWWMSpills())
+      MBB.addLiveIn(Reg.first);
+
+    MBB.sortUniqueLiveIns();
+  }
----------------
arsenm wrote:
> Actually, do we really need to do this anymore? If they were allocated from virtual registers, they should have correct livens lists already 
They are needed for prolog/epilog spill insertion. If we don't mark them liveIn, there will be a MIR verifier error indicating the use of undefined registers in spill instructions.



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  https://reviews.llvm.org/D124195/new/

https://reviews.llvm.org/D124195