[PATCH] D124195: [AMDGPU] Separate out SGPR spills to VGPR lanes during PEI
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 18:59:11 PDT 2022
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1295-1301
+ // Mark all lane VGPRs as BB LiveIns.
+ for (MachineBasicBlock &MBB : MF) {
+ for (auto &Reg : MFI->getWWMSpills())
+ MBB.addLiveIn(Reg.first);
+
+ MBB.sortUniqueLiveIns();
+ }
----------------
Actually, do we really need to do this anymore? If they were allocated from virtual registers, they should have correct livens lists already
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124195/new/
https://reviews.llvm.org/D124195
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