[PATCH] D136922: [AMDGPU][GISel] Widen s16 SHUFFLE_VECTOR where there are no scalar pack insts
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 13:22:01 PDT 2022
arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.
LGTM with nit
================
Comment at: llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:732
+ getDefSrcRegIgnoringCopies(DefReg, MRI);
+ assert(DefSrcReg);
+ DefReg = DefSrcReg->Reg;
----------------
This is redundant with the assert in operator->
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D136922/new/
https://reviews.llvm.org/D136922
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