[PATCH] D137190: [DAG] Allow scalable vectors in SimplifyDemanded routines
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 13:19:35 PDT 2022
reames created this revision.
reames added reviewers: craig.topper, frasercrmck, asb, efriedma.
Herald added subscribers: StephenFan, bollu, hiraditya, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added a subscriber: alextsao1999.
Herald added a project: LLVM.
This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.
The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D137190
Files:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AArch64/active_lane_mask.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
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