[PATCH] D137155: [MIRVRegNamer] Avoid opcode hash collision

[John Brawn via Phabricator via llvm-commits]

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D121929 <https://reviews.llvm.org/D121929> happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due to a hash collision caused by adding two extra opcodes. The collision is only in the top 19 bits of the hashed opcode so fix this by just using the whole hash (in fixed width hex for consistency) instead of the top 5 decimal digits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137155

Files:
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir
  llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
  llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
  llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
  llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
  llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir
  llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

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