[PATCH] D136680: [AArch64][SVE2] Add the SVE2.1 contiguous load to multiple consecutive vector

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3911-3916
+  if (RK == RegKind::SVEPredicateAsCounter && Pred != "z") {
+    Error(getLoc(), "expecting 'z' predication");
+    return MatchOperand_ParseFail;
+  }
+
+  if (RK == RegKind::SVEPredicateVector && Pred != "z" && Pred != "m") {
----------------
To be honest I don't see much value in this change.  It's not really true that `SVEPredicateVector` generally expects 'm' or 'z' because in reality few instructions support `z` and even less support both `z` and `m`. For example:
```
add     z23.b, p3/j, z23.b, z13.b
add     z23.b, p3/z, z23.b, z13.b
add     z23.b, p3/m, z23.b, z13.b
```
gives:
```
	.text
<stdin>:1:19: error: expecting 'm' or 'z' predication
add     z23.b, p3/j, z23.b, z13.b
                  ^
<stdin>:2:19: error: invalid operand for instruction
add     z23.b, p3/z, z23.b, z13.b
                  ^
	add	z23.b, p3/m, z23.b, z13.b       // encoding: [0xb7,0x0d,0x00,0x04]
```
This is the precedent set for predicate diagnostics and whilst not perfect I don't see a massive reason for `SVEPredicateAsCounter` to diverge. Especially given as soon as `m` support is required, removing this change will likely be the chosen fix.



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136680/new/

https://reviews.llvm.org/D136680