[PATCH] D136680: [AArch64][SVE2] Add the SVE2.1 contiguous load to multiple consecutive vector

[David Sherwood via Phabricator via llvm-commits]

david-arm marked 2 inline comments as done.
david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3884-3899
+  // Not all predicates are followed by a '/z'.
+  MCAsmParser &Parser = getParser();
+  if (Parser.getTok().isNot(AsmToken::Slash))
+    return MatchOperand_Success;
+
+  // But when they do they shouldn't have an element type suffix.
+  if (!Kind.empty()) {
----------------
paulwalker-arm wrote:
> Is there now sufficient commonality that you can reuse `tryParseSVEPredicateVector` and just pass in the register kind or have that as a template parameter?  I know this only requires "\z" support, but I don't think that really matters does it?
It's not as straightforward to reuse as it looks, because:

1) We want an error message for "pn/m", whereas "/m" is valid for normal predicates, and
2) The parsing of predicate indices is slightly different for each, i.e. "[w12, 0]" is a valid index for predicates (e.g. `psel    p0, p0, p0.b[w12, 0]`), but not for predicate-as-counters.

I've tried my best to reuse the code though, with some minor template-specialisations.


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  https://reviews.llvm.org/D136680/new/

https://reviews.llvm.org/D136680