[llvm] 99f9bd4 - [SLP]Fix a crash in the analysis of the compatible cmp operands.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2022-10-31T09:47:25-07:00
New Revision: 99f9bd4807d6132b603a1910902e4586e20638e0

URL: https://github.com/llvm/llvm-project/commit/99f9bd4807d6132b603a1910902e4586e20638e0
DIFF: https://github.com/llvm/llvm-project/commit/99f9bd4807d6132b603a1910902e4586e20638e0.diff

LOG: [SLP]Fix a crash in the analysis of the compatible cmp operands.

We can skip the analysis of the operands opcodes, can compare directly
them in some cases.

Added: 
    llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index d06ca6eeade1c..ba60ae7c7b7b9 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -547,6 +547,7 @@ static bool areCompatibleCmpOps(Value *BaseOp0, Value *BaseOp1, Value *Op0,
          (isConstant(BaseOp1) && isConstant(Op1)) ||
          (!isa<Instruction>(BaseOp0) && !isa<Instruction>(Op0) &&
           !isa<Instruction>(BaseOp1) && !isa<Instruction>(Op1)) ||
+         BaseOp0 == Op0 || BaseOp1 == Op1 ||
          getSameOpcode({BaseOp0, Op0}, TLI).getOpcode() ||
          getSameOpcode({BaseOp1, Op1}, TLI).getOpcode();
 }

diff  --git a/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll b/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
new file mode 100644
index 0000000000000..061fbdb45a13b
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s
+
+define i32 @alt_cmp(i16 %call46) {
+; CHECK-LABEL: @alt_cmp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CALL47:%.*]] = tail call i16 null(i16 0)
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL46:%.*]], i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL47]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i16>
+; CHECK-NEXT:    [[TMP6:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP5]])
+; CHECK-NEXT:    [[OP_RDX:%.*]] = or i16 [[TMP6]], 0
+; CHECK-NEXT:    [[EXT:%.*]] = zext i16 [[OP_RDX]] to i32
+; CHECK-NEXT:    ret i32 [[EXT]]
+;
+entry:
+  %0 = icmp ult i16 0, 0
+  %cond40 = zext i1 %0 to i16
+  %add41 = or i16 0, %cond40
+  %call47 = tail call i16 null(i16 0)
+  %.not299 = icmp ugt i16 %call46, %call47
+  %cond60 = zext i1 %.not299 to i16
+  %add61 = or i16 %add41, %cond60
+  %1 = icmp ugt i16 0, 0
+  %cond76 = zext i1 %1 to i16
+  %add77 = or i16 %add61, %cond76
+  %2 = icmp ult i16 0, 0
+  %cond144 = zext i1 %2 to i16
+  %add145 = or i16 %add77, %cond144
+  %ext = zext i16 %add145 to i32
+  ret i32 %ext
+}