[PATCH] D137066: [AMDGPU] Add amdgcn_s_buffer_load_imm intrinsic

[Piotr Sobczak via Phabricator via llvm-commits]

piotr created this revision.
Herald added subscribers: kosarev, foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
Herald added a project: All.
piotr requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Add int_amdgcn_s_buffer_load_imm instinsic for gfx9+, similar
to the existing int_amdgcn_s_buffer_load, but with immediate
instruction offset.

This exposes an immediate field of the instruction to the front-ends,
and can potentially help generate better code, especially in cases
of complex address expressions where the offset is located in
a different block than the load.

Basic handling also added in the global-isel path, but proper
support will be added in a separate patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137066

Files:
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SMInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.imm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D137066.471941.patch
Type: text/x-patch
Size: 60927 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221031/f122ad48/attachment.bin>