[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

Fri Oct 28 00:50:08 PDT 2022

cdevadas added a comment.

In D124192#3890769 <https://reviews.llvm.org/D124192#3890769>, @ruiling wrote:

> I am confused why the parent/child relationship among the changes are removed, I think there are still some dependencies among this and other changes?

Sorry about that. I have set them initially. But later broke the chain while arc patching them into a downstream compiler copy. The arc patch was causing trouble as it patches all reviews in the relationship chain when there are conflicts in the intermediate patches.
I put them back now. This is the parent review and there are other 9 patches in the chain ending at D124196 <https://reviews.llvm.org/D124196>.

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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1273
+      // that won't really need any such special handling.
+      if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32)
+        MFI->allocateWWMSpill(MF, MI.getOperand(0).getReg());
----------------
ruiling wrote:
> Why not define a separate pseudo instruction like V_SPILL_SGPR_TO_VGPR, which will be translated to V_WRITELANE at expandPostRAPseudo()? This should help us differentiate a writelane/readlane that have no wwm behavior from the sgpr spill/reload to vgpr.
Yes, that appeared to be a better approach than looking for WRITELANE/READLANE directly. Still, the looping is an overhead and we should move it entirely from here. Capturing them during the regalloc would be the efficient way. I'm planning a post-patch to optimize it.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192