[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

I am confused why the parent/child relationship among the changes are removed, I think there are still some dependencies among this and other changes?



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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1273
+      // that won't really need any such special handling.
+      if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32)
+        MFI->allocateWWMSpill(MF, MI.getOperand(0).getReg());
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Why not define a separate pseudo instruction like V_SPILL_SGPR_TO_VGPR, which will be translated to V_WRITELANE at expandPostRAPseudo()? This should help us differentiate a writelane/readlane that have no wwm behavior from the sgpr spill/reload to vgpr.


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  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192